Commit 0da310e8 authored by Zong Li's avatar Zong Li Committed by Paul Walmsley

riscv: gcov: enable gcov for RISC-V

This patch enables GCOV code coverage measurement on RISC-V.
Lightly tested on QEMU and Hifive Unleashed board, seems to work as
expected.
Signed-off-by: default avatarZong Li <zong.li@sifive.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Acked-by: default avatarJonathan Corbet <corbet@lwn.net>
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
parent ac51e005
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |
| powerpc: | ok | | powerpc: | ok |
| riscv: | TODO | | riscv: | ok |
| s390: | ok | | s390: | ok |
| sh: | ok | | sh: | ok |
| sparc: | TODO | | sparc: | TODO |
......
...@@ -64,6 +64,7 @@ config RISCV ...@@ -64,6 +64,7 @@ config RISCV
select SPARSEMEM_STATIC if 32BIT select SPARSEMEM_STATIC if 32BIT
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_MMAP_RND_BITS if MMU
select ARCH_HAS_GCOV_PROFILE_ALL
config ARCH_MMAP_RND_BITS_MIN config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT default 18 if 64BIT
......
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