Commit 0e2e212c authored by James Simmons's avatar James Simmons

Anothe rattempt at commting.

parent 864d65fb
Intel 810/815 Framebuffer driver
Tony Daplas <adaplas@pol.net>
http://i810fb.sourceforge.net
March 17, 2002
First Released: July 2001
================================================================
A. Introduction
This is a framebuffer driver for various Intel 810/815 compatible
graphics devices. These would include:
Intel 810
Intel 810E
Intel 810-DC100
Intel 815 Internal graphics only, 100Mhz FSB
Intel 815 Internal graphics only
Intel 815 Internal graphics and AGP
B. Features
- Choice of using Discrete Video Timings, VESA Generalized Timing
Formula, or a framebuffer specific database to set the video mode
- Supports a variable range of horizontal and vertical resolution, and
vertical refresh rates if the VESA Generalized Timing Formula is
enabled.
- Supports color depths of 8, 16, 24 and 32 bits per pixel
- Supports pseudocolor, directcolor, or truecolor visuals
- Full and optimized hardware acceleration at 8, 16 and 24 bpp
- Robust video state save and restore
- MTRR support
- Utilizes user-entered monitor specifications to automatically
calculate required video mode parameters.
- Can concurrently run with xfree86 running with native i810 drivers
- Hardware Cursor Support
C. List of available options
a. "video=i810fb"
enables the i810 driver
Recommendation: required
b. "xres:<value>"
select horizontal resolution in pixels
Recommendation: user preference
(default = 640)
c. "yres:<value>"
select vertical resolution in scanlines. If Discrete Video Timings
is enabled, this will be ignored and computed as 3*xres/4.
Recommendation: user preference
(default = 480)
d. "vyres:<value>"
select virtual vertical resolution in scanlines. If (0) or none
is specified, this will be computed against maximum available memory.
Recommendation: do not set
(default = 480)
e. "vram:<value>"
select amount of system RAM in MB to allocate for the video memory
Recommendation: 1 - 4 MB.
(default = 4)
f. "bpp:<value>"
select desired pixel depth
Recommendation: 8
(default = 8)
g. "hsync1/hsync2:<value>"
select the minimum and maximum Horizontal Sync Frequency of the
monitor in KHz. If a using a fixed frequency monitor, hsync1 must
be equal to hsync2.
Recommendation: check monitor manual for correct values
default (29/30)
h. "vsync1/vsync2:<value>"
select the minimum and maximum Vertical Sync Frequency of the monitor
in Hz. You can also use this option to lock your monitor's refresh
rate.
Recommendation: check monitor manual for correct values
(default = 60/60)
IMPORTANT: If you need to clamp your timings, try to give some
leeway for computational errors (over/underflows). Example: if
using vsync1/vsync2 = 60/60, make sure hsync1/hsync2 has at least
a 1 unit difference, and vice versa.
i. "voffset:<value>"
select at what offset in MB of the logical memory to allocate the
framebuffer memory. The intent is to avoid the memory blocks
used by standard graphics applications (XFree86). The default
offset (16 MB for a 64MB aperture, 8 MB for a 32MB aperture) will
avoid XFree86's usage and allows up to 7MB/15MB of framebuffer
memory. Depending on your usage, adjust the value up or down,
(0 for maximum usage, 31/63 MB for the least amount). Note, an
arbitrary setting may conflict with XFree86.
Recommendation: do not set
(default = 8 or 16 MB)
j. "accel"
enable text acceleration. This can be enabled/reenabled anytime
by using 'fbset -accel true/false'.
Recommendation: enable
(default = not set)
k. "mtrr"
enable MTRR. This allows data transfers to the framebuffer memory
to occur in bursts which can significantly increase performance.
Not very helpful with the i810/i815 because of 'shared memory'.
Recommendation: do not set
(default = not set)
l. "extvga"
if specified, secondary/external VGA output will always be enabled.
Useful if the BIOS turns off the VGA port when no monitor is attached.
The external VGA monitor can then be attached without rebooting.
Recommendation: do not set
(default = not set)
m. "sync"
Forces the hardware engine to do a "sync" or wait for the hardware
to finish before starting another instruction. This will produce a
more stable setup, but will be slower.
Recommendation: do not set
(default = not set)
n. "dcolor"
Use directcolor visual instead of truecolor for pixel depths greater
than 8 bpp. Useful for color tuning, such as gamma control.
Recommendation: do not set
(default = not set)
D. Kernel booting
Separate each option/option-pair by commas (,) and the option from its value
with a colon (:) as in the following:
video=i810fb:option1,option2:value2
Sample Usage
------------
In /etc/lilo.conf, add the line:
append="video=i810fb:vram:2,xres:1024,yres:768,bpp:8,hsync1:30,hsync2:55, \
vsync1:50,vsync2:85,accel,mtrr"
This will initialize the framebuffer to 1024x768 at 8bpp. The framebuffer
will use 2 MB of System RAM. MTRR support will be enabled. The refresh rate
will be computed based on the hsync1/hsync2 and vsync1/vsync2 values.
IMPORTANT:
You must include hsync1, hsync2, vsync1 and vsync2 to enable video modes
better than 640x480 at 60Hz.
E. Module options
The module parameters are essentially similar to the kernel
parameters. The main difference is that you need to include a Boolean value
(1 for TRUE, and 0 for FALSE) for those options which don't need a value.
Example, to enable MTRR, include "mtrr=1".
Sample Usage
------------
Using the same setup as described above, load the module like this:
modprobe i810fb vram=2 xres=1024 bpp=8 hsync1=30 hsync2=55 vsync1=50 \
vsync2=85 accel=1 mtrr=1
Or just add the following to /etc/modules.conf
options i810fb vram=2 xres=1024 bpp=16 hsync1=30 hsync2=55 vsync1=50 \
vsync2=85 accel=1 mtrr=1
and just do a
modprobe i810fb
F. Setup
a. Do your usual method of configuring the kernel.
make menuconfig/xconfig/config
b. Under "Code Maturity Options", enable "Prompt for experimental/
incomplete code/drivers".
c. Enable agpgart support for the Intel 810/815 on-board graphics.
This is required. The option is under "Character Devices"
d. Under "Graphics Support", select "Intel 810/815" either statically
or as a module. Choose "use VESA GTF for video timings" if you
need to maximize the capability of your display. To be on the
safe side, you can leave this unselected.
e. If you want a framebuffer console, enable it under "Console
Drivers"
f. Compile your kernel.
g. Load the driver as described in section D and E.
Optional:
h. If you are going to run XFree86 with its native drivers, the
standard XFree86 4.1.0 and 4.2.0 drivers should work as is.
However, there's a bug in the XFree86 i810 drivers. It attempts
to use XAA even when switched to the console. This will crash
your server. I have a fix at this site:
http://i810fb.sourceforge.net.
You can either use the patch, or just replace
/usr/X11R6/lib/modules/drivers/i810_drv.o
with the one provided at the website.
i. Try the DirectFB (http://www.directfb.org) + the i810 gfxdriver
patch to see the chipset in action (or inaction :-).
G. Acknowledgment:
1. Geert Uytterhoeven - his excellent howto and the virtual
framebuffer driver code made this possible.
2. Jeff Hartmann for his agpgart code.
3. The X developers. Insights were provided just by reading the
XFree86 source code.
4. Intel(c). For this value-oriented chipset driver and for
providing documentation.
5. Matt Sottek. His inputs and ideas helped in making some
optimizations possible.
H. Home Page:
A more complete, and probably updated information is provided at
http://i810fb.sourceforge.net.
###########################
Tony
......@@ -471,6 +471,44 @@ config FB_RIVA
module will be called rivafb.o. If you want to compile it as a
module, say M here and read <file:Documentation/modules.txt>.
config FB_I810
tristate "Intel 810/815 support (EXPERIMENTAL)"
depends on FB && AGP && AGP_INTEL && EXPERIMENTAL && PCI
help
This driver supports the on-board graphics built in to the Intel 810
and 815 chipsets. Say Y if you have and plan to use such a board.
The driver is also available as a module ( = code which can be
inserted and removed from the running kernel whenever you want).
The module will be called i810fb.o. If you want to compile it as a
module, say M here and read <file:Documentation/modules.txt>.
For more information, please read
<file:Documentation/fb/intel810.txt>
config FB_I810_GTF
bool "use VESA Generalized Timing Formula"
depends on FB_I810
help
If you say Y, then the VESA standard, Generalized Timing Formula
or GTF, will be used to calculate the required video timing values
per video mode. Since the GTF allows nondiscrete timings
(nondiscrete being a range of values as opposed to discrete being a
set of values), you'll be able to use any combination of horizontal
and vertical resolutions, and vertical refresh rates without having
to specify your own timing parameters. This is especially useful
to maximize the performance of an aging display, or if you just
have a display with nonstandard dimensions. A VESA compliant
monitor is recommended, but can still work with non-compliant ones.
If you need or want this, then select this option. The timings may
not be compliant with Intel's recommended values. Use at your own
risk.
If you say N, the driver will revert to discrete video timings
using a set recommended by Intel in their documentation.
If unsure, say N.
config FB_MATROX
tristate "Matrox acceleration"
depends on FB && PCI
......
......@@ -12,8 +12,7 @@ export-objs := fbmem.o fbcmap.o fbmon.o modedb.o softcursor.o cfbfillrect.o
obj-$(CONFIG_VT) += console/
# Add fbmon.o back into obj-$(CONFIG_FB) in 2.5.x
obj-$(CONFIG_FB) += fbmem.o fbcmap.o modedb.o softcursor.o
obj-$(CONFIG_FB) += fbmem.o fbmon.o fbcmap.o modedb.o softcursor.o
# Only include macmodes.o if we have FB support and are PPC
ifeq ($(CONFIG_FB),y)
obj-$(CONFIG_PPC) += macmodes.o
......@@ -42,7 +41,7 @@ obj-$(CONFIG_FB_SGIVW) += sgivwfb.o cfbfillrect.o cfbcopyarea.o cfbim
obj-$(CONFIG_FB_3DFX) += tdfxfb.o
obj-$(CONFIG_FB_MAC) += macfb.o macmodes.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o
obj-$(CONFIG_FB_HP300) += hpfb.o cfbfillrect.o cfbimgblt.o
obj-$(CONFIG_FB_OF) += offb.o cfbfillrect.o cfbimgblit.o cfbcopyarea.o
obj-$(CONFIG_FB_OF) += offb.o cfbfillrect.o cfbimgblt.o cfbcopyarea.o
obj-$(CONFIG_FB_IMSTT) += imsttfb.o
obj-$(CONFIG_FB_RETINAZ3) += retz3fb.o
obj-$(CONFIG_FB_CLGEN) += clgenfb.o
......@@ -74,6 +73,8 @@ obj-$(CONFIG_FB_RIVA) += riva/ cfbfillrect.o cfbcopyarea.o \
cfbimgblt.o vgastate.o
obj-$(CONFIG_FB_SIS) += sis/
obj-$(CONFIG_FB_ATY) += aty/ cfbimgblt.o
obj-$(CONFIG_FB_I810) += i810/ cfbfillrect.o cfbcopyarea.o \
cfbimgblt.o vgastate.o
obj-$(CONFIG_FB_SUN3) += sun3fb.o
obj-$(CONFIG_FB_BWTWO) += bwtwofb.o
......
......@@ -976,7 +976,7 @@ static int atyfb_release(struct fb_info *info, int user)
var.yres_virtual =
var.yres;
}
gen_set_var(&var, -1, info);
fb_set_var(&var, -1, info);
}
}
}
......
......@@ -103,10 +103,10 @@ static inline void color_imageblit(struct fb_image *image, struct fb_info *p, u8
{
/* Draw the penguin */
int i, n;
unsigned long bitmask = SHIFT_LOW(~0UL, BITS_PER_LONG - p->var.bits_per_pixel);
int bpp = p->var.bits_per_pixel;
unsigned long *palette = (unsigned long *) p->pseudo_palette;
unsigned long *dst, *dst2, color = 0, val, shift;
unsigned long null_bits = BITS_PER_LONG - p->var.bits_per_pixel;
unsigned long null_bits = BITS_PER_LONG - bpp;
u8 *src = image->data;
dst2 = (unsigned long *) dst1;
......@@ -125,9 +125,10 @@ static inline void color_imageblit(struct fb_image *image, struct fb_info *p, u8
while (n--) {
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR )
color = palette[*src] & bitmask;
color = palette[*src];
else
color = *src & bitmask;
color = *src;
color <<= LEFT_POS(bpp);
val |= SHIFT_HIGH(color, shift);
if (shift >= null_bits) {
FB_WRITEL(val, dst++);
......@@ -136,7 +137,7 @@ static inline void color_imageblit(struct fb_image *image, struct fb_info *p, u8
else
val = SHIFT_LOW(color, BITS_PER_LONG - shift);
}
shift += p->var.bits_per_pixel;
shift += bpp;
shift &= (BITS_PER_LONG - 1);
src++;
}
......
......@@ -929,11 +929,11 @@ static void fbcon_set_display(int con, int init, int logo)
struct display *q = &fb_display[i];
struct vc_data *tmp = vc_cons[i].d;
if (fontwidthvalid(p, vc->vc_font.width)) {
if (!fontwidthvalid(p, vc->vc_font.width)) {
/* If we are not the first console on this
fb, copy the font from that console */
tmp->vc_font.width = vc->vc_font.width;
tmp->vc_font.height = vc->vc_font.height;
vc->vc_font.width = tmp->vc_font.width;
vc->vc_font.height = tmp->vc_font.height;
p->fontdata = q->fontdata;
p->userfont = q->userfont;
if (p->userfont) {
......
......@@ -141,6 +141,8 @@ extern int pvr2fb_init(void);
extern int pvr2fb_setup(char*);
extern int sstfb_init(void);
extern int sstfb_setup(char*);
extern int i810fb_init(void);
extern int i810fb_setup(char*);
static struct {
const char *name;
......@@ -235,6 +237,9 @@ static struct {
#ifdef CONFIG_FB_TRIDENT
{ "trident", tridentfb_init, tridentfb_setup },
#endif
#ifdef CONFIG_FB_I810
{ "i810fb", i810fb_init, i810fb_setup },
#endif
/*
* Generic drivers that are used as fallbacks
......
This diff is collapsed.
/*-*- linux-c -*-
* linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
*
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
* All Rights Reserved
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef __I810_H__
#define __I810_H__
#include <linux/list.h>
#include <linux/agp_backend.h>
#include <linux/fb.h>
#include <video/vga.h>
/* Fence */
#define TILEWALK_X (0 << 12)
#define TILEWALK_Y (1 << 12)
/* Raster ops */
#define COLOR_COPY_ROP 0xF0
#define PAT_COPY_ROP 0xCC
#define CLEAR_ROP 0x00
#define WHITE_ROP 0xFF
#define INVERT_ROP 0x55
#define XOR_ROP 0x5A
/* 2D Engine definitions */
#define SOLIDPATTERN 0x80000000
#define NONSOLID 0x00000000
#define BPP8 (0 << 24)
#define BPP16 (1 << 24)
#define BPP24 (2 << 24)
#define PIXCONF8 (2 << 16)
#define PIXCONF15 (4 << 16)
#define PIXCONF16 (5 << 16)
#define PIXCONF24 (6 << 16)
#define PIXCONF32 (7 << 16)
#define DYN_COLOR_EN (1 << 26)
#define DYN_COLOR_DIS (0 << 26)
#define INCREMENT 0x00000000
#define DECREMENT (0x01 << 30)
#define ARB_ON 0x00000001
#define ARB_OFF 0x00000000
#define SYNC_FLIP 0x00000000
#define ASYNC_FLIP 0x00000040
#define OPTYPE_MASK 0xE0000000
#define PARSER_MASK 0x001F8000
#define D2_MASK 0x001FC000 /* 2D mask */
/* Instruction type */
/* There are more but pertains to 3D */
#define PARSER 0x00000000
#define BLIT (0x02 << 29)
#define RENDER (0x03 << 29)
/* Parser */
#define NOP 0x00 /* No operation, padding */
#define BP_INT (0x01 << 23) /* Breakpoint interrupt */
#define USR_INT (0x02 << 23) /* User interrupt */
#define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
#define FLUSH (0x04 << 23)
#define CONTEXT_SEL (0x05 << 23)
#define REPORT_HEAD (0x07 << 23)
#define ARB_ON_OFF (0x08 << 23)
#define OVERLAY_FLIP (0x11 << 23)
#define LOAD_SCAN_INC (0x12 << 23)
#define LOAD_SCAN_EX (0x13 << 23)
#define FRONT_BUFFER (0x14 << 23)
#define DEST_BUFFER (0x15 << 23)
#define Z_BUFFER (0x16 << 23)
#define STORE_DWORD_IMM (0x20 << 23)
#define STORE_DWORD_IDX (0x21 << 23)
#define BATCH_BUFFER (0x30 << 23)
/* Blit */
#define SETUP_BLIT 0x00
#define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
#define PIXEL_BLT (0x20 << 22)
#define SCANLINE_BLT (0x21 << 22)
#define TEXT_BLT (0x22 << 22)
#define TEXT_IMM_BLT (0x30 << 22)
#define COLOR_BLT (0x40 << 22)
#define MONO_PAT_BLIT (0x42 << 22)
#define SOURCE_COPY_BLIT (0x43 << 22)
#define MONO_SOURCE_COPY_BLIT (0x44 << 22)
#define SOURCE_COPY_IMMEDIATE (0x60 << 22)
#define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
#define VERSION_MAJOR 0
#define VERSION_MINOR 9
#define VERSION_TEENIE 0
#define BRANCH_VERSION ""
/* mvo: intel i815 */
#ifndef PCI_DEVICE_ID_INTEL_82815_100
#define PCI_DEVICE_ID_INTEL_82815_100 0x1102
#endif
#ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
#define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
#endif
#ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
#define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
#endif
/* General Defines */
#define I810_PAGESIZE 4096
#define MAX_DMA_SIZE (1024 * 4096)
#define SAREA_SIZE 4096
#define PCI_I810_MISCC 0x72
#define MMIO_SIZE (512*1024)
#define GTT_SIZE (16*1024)
#define RINGBUFFER_SIZE (64*1024)
#define PIXMAP_SIZE (4 * 4096)
#define CURSOR_SIZE 4096
#define OFF 0
#define ON 1
#define MAX_KEY 256
#define WAIT_COUNT 10000000
#define IRING_PAD 8
#define FONTDATAMAX 8192
/* Masks (AND ops) and OR's */
#define FB_START_MASK (0x3f << (32 - 6))
#define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
#define FREQ_MASK 0x1EF
#define SCR_OFF 0x20
#define DRAM_ON 0x08
#define DRAM_OFF 0xE7
#define PG_ENABLE_MASK 0x01
#define RING_SIZE_MASK (RINGBUFFER_SIZE - 1);
/* defines for restoring registers partially */
#define ADDR_MAP_MASK (0x07 << 5)
#define DISP_CTRL ~0
#define PIXCONF_0 (0x64 << 8)
#define PIXCONF_2 (0xF3 << 24)
#define PIXCONF_1 (0xF0 << 16)
#define MN_MASK 0x3FF03FF
#define P_OR (0x7 << 4)
#define DAC_BIT (1 << 16)
#define INTERLACE_BIT (1 << 7)
#define IER_MASK (3 << 13)
#define IMR_MASK (3 << 13)
/* Power Management */
#define DPMS_MASK 0xF0000
#define POWERON 0x00000
#define STANDBY 0x20000
#define SUSPEND 0x80000
#define POWERDOWN 0xA0000
#define EMR_MASK ~0x3F
#define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
/* Ringbuffer */
#define RBUFFER_START_MASK 0xFFFFF000
#define RBUFFER_SIZE_MASK 0x001FF000
#define RBUFFER_HEAD_MASK 0x001FFFFC
#define RBUFFER_TAIL_MASK 0x001FFFF8
/* Video Timings */
#define REF_FREQ 24000000
#define TARGET_N_MAX 30
#define FLYBACK 550
#define V_FRONTPORCH 1
#define H_OFFSET 40
#define H_SCALEFACTOR 20
#define H_BLANKSCALE 128
#define H_GRADIENT 600
#define MAX_PIXELCLOCK 230000000
#define MIN_PIXELCLOCK 15000000
#define VFMAX 60
#define VFMIN 60
#define HFMAX 30000
#define HFMIN 29000
/* Cursor */
#define CURSOR_ENABLE_MASK 0x1000
#define CURSOR_MODE_64_TRANS 4
#define CURSOR_MODE_64_XOR 5
#define CURSOR_MODE_64_3C 6
#define COORD_INACTIVE 0
#define COORD_ACTIVE (1 << 4)
#define EXTENDED_PALETTE 1
/* AGP Memory Types*/
#define AGP_NORMAL_MEMORY 0
#define AGP_DCACHE_MEMORY 1
#define AGP_PHYSICAL_MEMORY 2
/* Allocated resource Flags */
#define FRAMEBUFFER_REQ 1
#define MMIO_REQ 2
#define PCI_DEVICE_ENABLED 4
#define HAS_FONTCACHE 8
/* driver flags */
#define HAS_MTRR 1
#define HAS_ACCELERATION 2
#define ALWAYS_SYNC 4
#define LOCKUP 8
struct gtt_data {
agp_memory *i810_fb_memory;
agp_memory *i810_iring_memory;
agp_memory *i810_cursor_memory;
agp_memory *i810_pixmap_memory;
};
struct mode_registers {
u32 pixclock, M, N, P;
u8 cr00, cr01, cr02, cr03;
u8 cr04, cr05, cr06, cr07;
u8 cr09, cr10, cr11, cr12;
u8 cr13, cr15, cr16, cr30;
u8 cr31, cr32, cr33, cr35, cr39;
u32 bpp8_100, bpp16_100;
u32 bpp24_100, bpp8_133;
u32 bpp16_133, bpp24_133;
u8 msr;
};
struct heap_data {
unsigned long physical;
__u8 *virtual;
u32 offset;
u32 size;
};
struct state_registers {
u32 dclk_1d, dclk_2d, dclk_0ds;
u32 pixconf, fw_blc, pgtbl_ctl;
u32 fence0, hws_pga, dplystas;
u16 bltcntl, hwstam, ier, iir, imr;
u8 cr00, cr01, cr02, cr03, cr04;
u8 cr05, cr06, cr07, cr08, cr09;
u8 cr10, cr11, cr12, cr13, cr14;
u8 cr15, cr16, cr17, cr80, gr10;
u8 cr30, cr31, cr32, cr33, cr35;
u8 cr39, cr41, cr70, sr01, msr;
};
struct i810fb_par {
struct mode_registers regs;
struct state_registers hw_state;
struct gtt_data i810_gtt;
struct fb_ops i810fb_ops;
struct pci_dev *dev;
struct heap_data aperture;
struct heap_data fb;
struct heap_data iring;
struct heap_data cursor_heap;
struct heap_data pixmap;
struct vgastate state;
drm_agp_t *drm_agp;
atomic_t use_count;
u32 pseudo_palette[17];
unsigned long mmio_start_phys;
u8 *mmio_start_virtual;
u32 cursor_reset;
u8 red[64];
u8 green[64];
u8 blue[64];
u32 pixmap_offset;
u32 pitch;
u32 pixconf;
u32 watermark;
u32 mem_freq;
u32 res_flags;
u32 dev_flags;
u32 cur_tail;
u32 depth;
u32 blit_bpp;
u32 ovract;
int mtrr_reg;
u16 bltcntl;
u8 interlace;
};
/*
* Register I/O
*/
#define i810_readb(where, mmio) readb(mmio + where)
#define i810_readw(where, mmio) readw(mmio + where)
#define i810_readl(where, mmio) readl(mmio + where)
#define i810_writeb(where, mmio, val) writeb(val, mmio + where)
#define i810_writew(where, mmio, val) writew(val, mmio + where)
#define i810_writel(where, mmio, val) writel(val, mmio + where)
#endif /* __I810_H__ */
This diff is collapsed.
This diff is collapsed.
/*-*- linux-c -*-
* linux/drivers/video/i810_main.h -- Intel 810 Nondiscrete Video Timings
* (VESA GTF)
*
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
* All Rights Reserved
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include "i810_regs.h"
#include "i810.h"
/*
* FIFO and Watermark tables - based almost wholly on i810_wmark.c in
* XFree86 v4.03 by Precision Insight. Slightly modified for integer
* operation, instead of float
*/
struct wm_info {
u32 freq;
u32 wm;
};
struct wm_info i810_wm_8_100[] = {
{ 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
{ 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
{ 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
{ 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
{ 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
{ 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
{ 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
{ 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
{ 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
{ 218, 0x2220f000 }, { 229, 0x22210000 }, { 234, 0x22210000 },
};
struct wm_info i810_wm_16_100[] = {
{ 15, 0x0070c000 }, { 19, 0x0020c000 }, { 25, 0x22006000 },
{ 28, 0x22006000 }, { 31, 0x22007000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
{ 50, 0x22009000 }, { 56, 0x22108000 }, { 65, 0x2210e000 },
{ 75, 0x2210e000 }, { 78, 0x2210e000 }, { 80, 0x22210000 },
{ 94, 0x22210000 }, { 96, 0x22210000 }, { 99, 0x22210000 },
{ 108, 0x22210000 }, { 121, 0x22210000 }, { 128, 0x22210000 },
{ 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
{ 162, 0x22416000 }, { 175, 0x22416000 }, { 189, 0x22416000 },
{ 195, 0x22416000 }, { 202, 0x22416000 }, { 204, 0x22416000 },
{ 218, 0x22416000 }, { 229, 0x22416000 },
};
struct wm_info i810_wm_24_100[] = {
{ 15, 0x0020c000 }, { 19, 0x0040c000 }, { 25, 0x22009000 },
{ 28, 0x22009000 }, { 31, 0x2200a000 }, { 36, 0x2210c000 },
{ 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
{ 50, 0x22111000 }, { 56, 0x22111000 }, { 65, 0x22214000 },
{ 75, 0x22214000 }, { 78, 0x22215000 }, { 80, 0x22216000 },
{ 94, 0x22218000 }, { 96, 0x22418000 }, { 99, 0x22418000 },
{ 108, 0x22418000 }, { 121, 0x22418000 }, { 128, 0x22419000 },
{ 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
{ 162, 0x44419000 }, { 175, 0x44419000 }, { 189, 0x44419000 },
{ 195, 0x44419000 }, { 202, 0x44419000 }, { 204, 0x44419000 },
};
struct wm_info i810_wm_8_133[] = {
{ 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
{ 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
{ 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
{ 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
{ 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
{ 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
{ 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
{ 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
{ 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
{ 218, 0x2220f000 }, { 229, 0x22210000 }, { 234, 0x22210000 },
};
struct wm_info i810_wm_16_133[] = {
{ 15, 0x0020c000 }, { 19, 0x0020c000 }, { 25, 0x22006000 },
{ 28, 0x22006000 }, { 31, 0x22007000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
{ 50, 0x22009000 }, { 56, 0x22108000 }, { 65, 0x2210e000 },
{ 75, 0x2210e000 }, { 78, 0x2210e000 }, { 80, 0x22210000 },
{ 94, 0x22210000 }, { 96, 0x22210000 }, { 99, 0x22210000 },
{ 108, 0x22210000 }, { 121, 0x22210000 }, { 128, 0x22210000 },
{ 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
{ 162, 0x22416000 }, { 175, 0x22416000 }, { 189, 0x22416000 },
{ 195, 0x22416000 }, { 202, 0x22416000 }, { 204, 0x22416000 },
{ 218, 0x22416000 }, { 229, 0x22416000 },
};
struct wm_info i810_wm_24_133[] = {
{ 15, 0x0020c000 }, { 19, 0x00408000 }, { 25, 0x22009000 },
{ 28, 0x22009000 }, { 31, 0x2200a000 }, { 36, 0x2210c000 },
{ 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
{ 50, 0x22111000 }, { 56, 0x22111000 }, { 65, 0x22214000 },
{ 75, 0x22214000 }, { 78, 0x22215000 }, { 80, 0x22216000 },
{ 94, 0x22218000 }, { 96, 0x22418000 }, { 99, 0x22418000 },
{ 108, 0x22418000 }, { 121, 0x22418000 }, { 128, 0x22419000 },
{ 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
{ 162, 0x44419000 }, { 175, 0x44419000 }, { 189, 0x44419000 },
{ 195, 0x44419000 }, { 202, 0x44419000 }, { 204, 0x44419000 },
};
void round_off_xres(u32 *xres) { }
void round_off_yres(u32 *xres, u32 *yres) { }
/**
* i810fb_encode_registers - encode @var to hardware register values
* @var: pointer to var structure
* @par: pointer to hardware par structure
*
* DESCRIPTION:
* Timing values in @var will be converted to appropriate
* register values of @par.
*/
void i810fb_encode_registers(const struct fb_var_screeninfo *var,
struct i810fb_par *par, u32 xres, u32 yres)
{
int n, blank_s, blank_e;
u8 *mmio = par->mmio_start_virtual, msr = 0;
/* Horizontal */
/* htotal */
n = ((xres + var->right_margin + var->hsync_len +
var->left_margin) >> 3) - 5;
par->regs.cr00 = (u8) n;
par->regs.cr35 = (u8) ((n >> 8) & 1);
/* xres */
par->regs.cr01 = (u8) ((xres >> 3) - 1);
/* hblank */
blank_e = (xres + var->right_margin + var->hsync_len +
var->left_margin) >> 3;
blank_e--;
blank_s = blank_e - 127;
if (blank_s < (xres >> 3))
blank_s = xres >> 3;
par->regs.cr02 = (u8) blank_s;
par->regs.cr03 = (u8) (blank_e & 0x1F);
par->regs.cr05 = (u8) ((blank_e & (1 << 5)) << 2);
par->regs.cr39 = (u8) ((blank_e >> 6) & 1);
/* hsync */
par->regs.cr04 = (u8) ((xres + var->right_margin) >> 3);
par->regs.cr05 |= (u8) (((xres + var->right_margin +
var->hsync_len) >> 3) & 0x1F);
/* Vertical */
/* vtotal */
n = yres + var->lower_margin + var->vsync_len + var->upper_margin - 2;
par->regs.cr06 = (u8) (n & 0xFF);
par->regs.cr30 = (u8) ((n >> 8) & 0x0F);
/* vsync */
n = yres + var->lower_margin;
par->regs.cr10 = (u8) (n & 0xFF);
par->regs.cr32 = (u8) ((n >> 8) & 0x0F);
par->regs.cr11 = i810_readb(CR11, mmio) & ~0x0F;
par->regs.cr11 |= (u8) ((yres + var->lower_margin +
var->vsync_len) & 0x0F);
/* yres */
n = yres - 1;
par->regs.cr12 = (u8) (n & 0xFF);
par->regs.cr31 = (u8) ((n >> 8) & 0x0F);
/* vblank */
blank_e = yres + var->lower_margin + var->vsync_len +
var->upper_margin;
blank_e--;
blank_s = blank_e - 127;
if (blank_s < yres)
blank_s = yres;
par->regs.cr15 = (u8) (blank_s & 0xFF);
par->regs.cr33 = (u8) ((blank_s >> 8) & 0x0F);
par->regs.cr16 = (u8) (blank_e & 0xFF);
par->regs.cr09 = 0;
/* sync polarity */
if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
msr |= 1 << 6;
if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
msr |= 1 << 7;
par->regs.msr = msr;
/* interlace */
if (var->vmode & FB_VMODE_INTERLACED)
par->interlace = (1 << 7) | ((u8) (var->yres >> 4));
else
par->interlace = 0;
if (var->vmode & FB_VMODE_DOUBLE)
par->regs.cr09 |= 1 << 7;
/* overlay */
par->ovract = ((var->xres + var->right_margin + var->hsync_len +
var->left_margin - 32) | ((var->xres - 32) << 16));
}
void i810fb_fill_var_timings(struct fb_var_screeninfo *var) { }
/**
* i810_get_watermark - gets watermark
* @var: pointer to fb_var_screeninfo
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Get's the required watermark based on
* pixelclock and RAMBUS frequency.
*
* RETURNS:
* watermark
*/
u32 i810_get_watermark(const struct fb_var_screeninfo *var,
struct i810fb_par *par)
{
struct wm_info *wmark = 0;
u32 i, size = 0, pixclock, wm_best = 0, min, diff;
if (par->mem_freq == 100) {
switch (var->bits_per_pixel) {
case 8:
wmark = i810_wm_8_100;
size = ARRAY_SIZE(i810_wm_8_100);
break;
case 16:
wmark = i810_wm_16_100;
size = ARRAY_SIZE(i810_wm_16_100);
break;
case 24:
case 32:
wmark = i810_wm_24_100;
size = ARRAY_SIZE(i810_wm_24_100);
}
}
else {
switch(var->bits_per_pixel) {
case 8:
wmark = i810_wm_8_133;
size = ARRAY_SIZE(i810_wm_8_133);
break;
case 16:
wmark = i810_wm_16_133;
size = ARRAY_SIZE(i810_wm_16_133);
break;
case 24:
case 32:
wmark = i810_wm_24_133;
size = ARRAY_SIZE(i810_wm_24_133);
}
}
pixclock = 1000000/var->pixclock;
min = ~0;
for (i = 0; i < size; i++) {
if (pixclock <= wmark[i].freq)
diff = wmark[i].freq - pixclock;
else
diff = pixclock - wmark[i].freq;
if (diff < min) {
wm_best = wmark[i].wm;
min = diff;
}
}
return wm_best;
}
This diff is collapsed.
/*-*- linux-c -*-
* linux/drivers/video/i810fb_main.h -- Intel 810 frame buffer device
* main header file
*
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
* All Rights Reserved
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef __I810_MAIN_H__
#define __I810_MAIN_H__
/* PCI */
static const char *i810_pci_list[] __devinitdata = {
"Intel(R) 810 Framebuffer Device" ,
"Intel(R) 810-DC100 Framebuffer Device" ,
"Intel(R) 810E Framebuffer Device" ,
"Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" ,
"Intel(R) 815 (Internal Graphics only) Framebuffer Device" ,
"Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
};
static struct pci_device_id i810fb_pci_tbl[] __devinitdata = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
/* mvo: added i815 PCI-ID */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }
};
static int __devinit i810fb_init_pci (struct pci_dev *dev,
const struct pci_device_id *entry);
static void __devexit i810fb_remove_pci(struct pci_dev *dev);
static struct pci_driver i810fb_driver = {
.name = "i810fb",
.id_table = i810fb_pci_tbl,
.probe = i810fb_init_pci,
.remove = __devexit_p(i810fb_remove_pci),
};
static int i810_init __devinitdata = 0;
static int vram __devinitdata = 4;
static int bpp __devinitdata = 8;
static int mtrr __devinitdata = 0;
static int accel __devinitdata = 0;
static int hsync1 __devinitdata = 0;
static int hsync2 __devinitdata = 0;
static int vsync1 __devinitdata = 0;
static int vsync2 __devinitdata = 0;
static int xres __devinitdata = 640;
static int yres __devinitdata = 480;
static int vyres __devinitdata = 0;
static int sync __devinitdata = 0;
static int ext_vga __devinitdata = 0;
static int dcolor __devinitdata = 0;
/* "use once" vars */
static char i810fb_name[16] = "i810fb";
static struct fb_var_screeninfo i810fb_default __devinitdata = {
/* 640x480, 8 bpp */
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.xoffset = 0,
.yoffset = 0,
.bits_per_pixel = 8,
.grayscale = 0,
.red = {0, 8, 0},
.green = {0, 8, 0},
.blue = {0, 8, 0},
.transp = {0, 0, 0},
.nonstd = 0,
.activate = 0,
.height = -1,
.width = -1,
.accel_flags = 0,
.pixclock = 20000,
.left_margin = 64,
.right_margin = 64,
.upper_margin = 32,
.lower_margin = 32,
.hsync_len = 64,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* voffset - framebuffer offset in MiB from aperture start address. In order for
* the driver to work with X, we must try to use memory holes left untouched by X. The
* following table lists where X's different surfaces start at.
*
* ---------------------------------------------
* : : 64 MiB : 32 MiB :
* ----------------------------------------------
* : FrontBuffer : 0 : 0 :
* : DepthBuffer : 48 : 16 :
* : BackBuffer : 56 : 24 :
* ----------------------------------------------
*
* So for chipsets with 64 MiB Aperture sizes, 32 MiB for v_offset is okay, allowing up to
* 15 + 1 MiB of Framebuffer memory. For 32 MiB Aperture sizes, a v_offset of 8 MiB should
* work, allowing 7 + 1 MiB of Framebuffer memory.
* Note, the size of the hole may change depending on how much memory you allocate to X,
* and how the memory is split up between these surfaces.
*
* Note: Anytime the DepthBuffer or FrontBuffer is overlapped, X would still run but with
* DRI disabled. But if the Frontbuffer is overlapped, X will fail to load.
*
* Experiment with v_offset to find out which works best for you.
*/
static u32 v_offset_default __devinitdata; /* For 32 MiB Aper size, 8 should be the default */
static u32 voffset __devinitdata = 0;
static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
/* Chipset Specific Functions */
static int i810fb_set_par (struct fb_info *info);
static int i810fb_getcolreg (u8 regno, u8 *red, u8 *green, u8 *blue,
u8 *transp, struct fb_info *info);
static int i810fb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info);
static int i810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
static int i810fb_blank (int blank_mode, struct fb_info *info);
/* Initialization */
static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par);
extern int __init agp_intel_init(void);
extern int __init agp_init(void);
/* Video Timings */
extern void round_off_xres (u32 *xres);
extern void round_off_yres (u32 *xres, u32 *yres);
extern u32 i810_get_watermark (const struct fb_var_screeninfo *var,
struct i810fb_par *par);
extern void i810fb_encode_registers(const struct fb_var_screeninfo *var,
struct i810fb_par *par, u32 xres, u32 yres);
extern void i810fb_fill_var_timings(struct fb_var_screeninfo *var);
/* Accelerated Functions */
extern void i810fb_fillrect (struct fb_info *p, struct fb_fillrect *rect);
extern void i810fb_copyarea (struct fb_info *p, struct fb_copyarea *region);
extern void i810fb_imageblit(struct fb_info *p, struct fb_image *image);
extern int i810fb_sync (struct fb_info *p);
extern void i810fb_init_ringbuffer (struct i810fb_par *par);
/* Conditionals */
#if defined(__i386__)
inline void flush_cache(void)
{
asm volatile ("wbinvd":::"memory");
}
#else
#define flush_cache() do { } while(0)
#endif
#ifdef CONFIG_MTRR
#define KERNEL_HAS_MTRR 1
static inline void __devinit set_mtrr(struct i810fb_par *par)
{
par->mtrr_reg = mtrr_add((u32) par->aperture.physical,
par->aperture.size, MTRR_TYPE_WRCOMB, 1);
if (par->mtrr_reg < 0) {
printk("set_mtrr: unable to set MTRR/n");
return;
}
par->dev_flags |= HAS_MTRR;
}
static inline void unset_mtrr(struct i810fb_par *par)
{
if (par->dev_flags & HAS_MTRR)
mtrr_del(par->mtrr_reg, (u32) par->aperture.physical,
par->aperture.size);
}
#else
#define KERNEL_HAS_MTRR 0
#define set_mtrr(x) printk("set_mtrr: MTRR is disabled in the kernel\n")
#define unset_mtrr(x) do { } while (0)
#endif /* CONFIG_MTRR */
#ifdef CONFIG_FB_I810_GTF
#define IS_DVT (0)
#else
#define IS_DVT (1)
#endif
#endif /* __I810_MAIN_H__ */
/*-*- linux-c -*-
* linux/drivers/video/i810_regs.h -- Intel 810/815 Register List
*
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
* All Rights Reserved
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/*
* Intel 810 Chipset Family PRM 15 3.1
* GC Register Memory Address Map
*
* Based on:
* Intel (R) 810 Chipset Family
* Programmer s Reference Manual
* November 1999
* Revision 1.0
* Order Number: 298026-001 R
*
* All GC registers are memory-mapped. In addition, the VGA and extended VGA registers
* are I/O mapped.
*/
#ifndef __I810_REGS_H__
#define __I810_REGS_H__
/* Instruction and Interrupt Control Registers (01000h 02FFFh) */
#define FENCE 0x02000
#define PGTBL_CTL 0x02020
#define PGTBL_ER 0x02024
#define LRING 0x02030
#define IRING 0x02040
#define HWS_PGA 0x02080
#define IPEIR 0x02088
#define IPEHR 0x0208C
#define INSTDONE 0x02090
#define NOPID 0x02094
#define HWSTAM 0x02098
#define IER 0x020A0
#define IIR 0x020A4
#define IMR 0x020A8
#define ISR 0x020AC
#define EIR 0x020B0
#define EMR 0x020B4
#define ESR 0x020B8
#define INSTPM 0x020C0
#define INSTPS 0x020C4
#define BBP_PTR 0x020C8
#define ABB_SRT 0x020CC
#define ABB_END 0x020D0
#define DMA_FADD 0x020D4
#define FW_BLC 0x020D8
#define MEM_MODE 0x020DC
/* Memory Control Registers (03000h 03FFFh) */
#define DRT 0x03000
#define DRAMCL 0x03001
#define DRAMCH 0x03002
/* Span Cursor Registers (04000h 04FFFh) */
#define UI_SC_CTL 0x04008
/* I/O Control Registers (05000h 05FFFh) */
#define HVSYNC 0x05000
#define GPIOA 0x05010
#define GPIOB 0x05014
/* Clock Control and Power Management Registers (06000h 06FFFh) */
#define DCLK_0D 0x06000
#define DCLK_1D 0x06004
#define DCLK_2D 0x06008
#define LCD_CLKD 0x0600C
#define DCLK_0DS 0x06010
#define PWR_CLKC 0x06014
/* Graphics Translation Table Range Definition (10000h 1FFFFh) */
#define GTT 0x10000
/* Overlay Registers (30000h 03FFFFh) */
#define OVOADDR 0x30000
#define DOVOSTA 0x30008
#define GAMMA 0x30010
#define OBUF_0Y 0x30100
#define OBUF_1Y 0x30104
#define OBUF_0U 0x30108
#define OBUF_0V 0x3010C
#define OBUF_1U 0x30110
#define OBUF_1V 0x30114
#define OVOSTRIDE 0x30118
#define YRGB_VPH 0x3011C
#define UV_VPH 0x30120
#define HORZ_PH 0x30124
#define INIT_PH 0x30128
#define DWINPOS 0x3012C
#define DWINSZ 0x30130
#define SWID 0x30134
#define SWIDQW 0x30138
#define SHEIGHT 0x3013F
#define YRGBSCALE 0x30140
#define UVSCALE 0x30144
#define OVOCLRCO 0x30148
#define OVOCLRC1 0x3014C
#define DCLRKV 0x30150
#define DLCRKM 0x30154
#define SCLRKVH 0x30158
#define SCLRKVL 0x3015C
#define SCLRKM 0x30160
#define OVOCONF 0x30164
#define OVOCMD 0x30168
#define AWINPOS 0x30170
#define AWINZ 0x30174
/* BLT Engine Status (40000h 4FFFFh) (Software Debug) */
#define BR00 0x40000
#define BRO1 0x40004
#define BR02 0x40008
#define BR03 0x4000C
#define BR04 0x40010
#define BR05 0x40014
#define BR06 0x40018
#define BR07 0x4001C
#define BR08 0x40020
#define BR09 0x40024
#define BR10 0x40028
#define BR11 0x4002C
#define BR12 0x40030
#define BR13 0x40034
#define BR14 0x40038
#define BR15 0x4003C
#define BR16 0x40040
#define BR17 0x40044
#define BR18 0x40048
#define BR19 0x4004C
#define SSLADD 0x40074
#define DSLH 0x40078
#define DSLRADD 0x4007C
/* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */
/* LCD/TV-Out */
#define HTOTAL 0x60000
#define HBLANK 0x60004
#define HSYNC 0x60008
#define VTOTAL 0x6000C
#define VBLANK 0x60010
#define VSYNC 0x60014
#define LCDTV_C 0x60018
#define OVRACT 0x6001C
#define BCLRPAT 0x60020
/* Display and Cursor Control Registers (70000h 7FFFFh) */
#define DISP_SL 0x70000
#define DISP_SLC 0x70004
#define PIXCONF 0x70008
#define PIXCONF1 0x70009
#define BLTCNTL 0x7000C
#define SWF 0x70014
#define DPLYBASE 0x70020
#define DPLYSTAS 0x70024
#define CURCNTR 0x70080
#define CURBASE 0x70084
#define CURPOS 0x70088
/* VGA Registers */
/* SMRAM Registers */
#define SMRAM 0x10
/* Graphics Control Registers */
#define GR_INDEX 0x3CE
#define GR_DATA 0x3CF
#define GR10 0x10
#define GR11 0x11
/* CRT Controller Registers */
#define CR_INDEX_MDA 0x3B4
#define CR_INDEX_CGA 0x3D4
#define CR_DATA_MDA 0x3B5
#define CR_DATA_CGA 0x3D5
#define CR30 0x30
#define CR31 0x31
#define CR32 0x32
#define CR33 0x33
#define CR35 0x35
#define CR39 0x39
#define CR40 0x40
#define CR41 0x41
#define CR42 0x42
#define CR70 0x70
#define CR80 0x80
#define CR81 0x82
/* Extended VGA Registers */
/* General Control and Status Registers */
#define ST00 0x3C2
#define ST01_MDA 0x3BA
#define ST01_CGA 0x3DA
#define FRC_READ 0x3CA
#define FRC_WRITE_MDA 0x3BA
#define FRC_WRITE_CGA 0x3DA
#define MSR_READ 0x3CC
#define MSR_WRITE 0x3C2
/* Sequencer Registers */
#define SR_INDEX 0x3C4
#define SR_DATA 0x3C5
#define SR01 0x01
#define SR02 0x02
#define SR03 0x03
#define SR04 0x04
#define SR07 0x07
/* Graphics Controller Registers */
#define GR00 0x00
#define GR01 0x01
#define GR02 0x02
#define GR03 0x03
#define GR04 0x04
#define GR05 0x05
#define GR06 0x06
#define GR07 0x07
#define GR08 0x08
/* Attribute Controller Registers */
#define ATTR_WRITE 0x3C0
#define ATTR_READ 0x3C1
/* VGA Color Palette Registers */
/* CLUT */
#define CLUT_DATA 0x3C9 /* DACDATA */
#define CLUT_INDEX_READ 0x3C7 /* DACRX */
#define CLUT_INDEX_WRITE 0x3C8 /* DACWX */
#define DACMASK 0x3C6
/* CRT Controller Registers */
#define CR00 0x00
#define CR01 0x01
#define CR02 0x02
#define CR03 0x03
#define CR04 0x04
#define CR05 0x05
#define CR06 0x06
#define CR07 0x07
#define CR08 0x08
#define CR09 0x09
#define CR0A 0x0A
#define CR0B 0x0B
#define CR0C 0x0C
#define CR0D 0x0D
#define CR0E 0x0E
#define CR0F 0x0F
#define CR10 0x10
#define CR11 0x11
#define CR12 0x12
#define CR13 0x13
#define CR14 0x14
#define CR15 0x15
#define CR16 0x16
#define CR17 0x17
#define CR18 0x18
#endif /* __I810_REGS_H__ */
......@@ -393,6 +393,7 @@ static void __init offb_init_fb(const char *name, const char *full_name,
struct fb_fix_screeninfo *fix;
struct fb_var_screeninfo *var;
struct fb_info *info;
int size;
if (!request_mem_region(res_start, res_size, "offb"))
return;
......@@ -421,7 +422,7 @@ static void __init offb_init_fb(const char *name, const char *full_name,
var = &info->var;
strcpy(fix->id, "OFfb ");
strncat(fix->id, name, sizeof(fix->id));
strncat(fix->id, name, sizeof(fix->id) - sizeof("OFfb "));
fix->id[sizeof(fix->id) - 1] = '\0';
var->xres = var->xres_virtual = width;
......@@ -522,8 +523,6 @@ static void __init offb_init_fb(const char *name, const char *full_name,
var->sync = 0;
var->vmode = FB_VMODE_NONINTERLACED;
strcpy(fix->id, "OFfb ");
strncat(fix->id, full_name, sizeof(fix->id));
info->node = NODEV;
info->fbops = &offb_ops;
info->screen_base = ioremap(address, fix->smem_len);
......
This diff is collapsed.
......@@ -97,6 +97,7 @@
#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
#define FB_ACCEL_I810 39 /* Intel 810/815 */
#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
......@@ -432,9 +433,11 @@ struct fb_info {
#define fb_readb(addr) (*(volatile u8 *) (addr))
#define fb_readw(addr) (*(volatile u16 *) (addr))
#define fb_readl(addr) (*(volatile u32 *) (addr))
#define fb_readq(addr) (*(volatile u64 *) (addr))
#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b))
#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b))
#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b))
#define fb_writeq(b,addr) (*(volatile u64 *) (addr) = (b))
#define fb_memset memset
#endif
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment