Commit 0ff5a481 authored by Dinh Nguyen's avatar Dinh Nguyen

ARM: dts: socfpga: fix register entry for timer3 on Arria10

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 9123e3a7
...@@ -821,7 +821,7 @@ timer2: timer2@ffd00000 { ...@@ -821,7 +821,7 @@ timer2: timer2@ffd00000 {
timer3: timer3@ffd00100 { timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd01000 0x100>; reg = <0xffd00100 0x100>;
clocks = <&l4_sys_free_clk>; clocks = <&l4_sys_free_clk>;
clock-names = "timer"; clock-names = "timer";
resets = <&rst L4SYSTIMER1_RESET>; resets = <&rst L4SYSTIMER1_RESET>;
......
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