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Commit 10b7ca7e authored by Alex Deucher's avatar Alex Deucher
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drm/radeon: clean up sumo_rlc_init() for code sharing 

This will eventually be shared with newer asics to
reduce code duplication.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 866d83de
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Showing with 113 additions and 108 deletions
drivers/gpu/drm/radeon/evergreen.c
View file @ 10b7ca7e
...@@ -3910,131 +3910,136 @@ int sumo_rlc_init(struct radeon_device *rdev) ...@@ -3910,131 +3910,136 @@ int sumo_rlc_init(struct radeon_device *rdev)
dws = rdev->rlc.reg_list_size; dws = rdev->rlc.reg_list_size;
cs_data = rdev->rlc.cs_data; cs_data = rdev->rlc.cs_data;
/* save restore block */ if (src_ptr) {
if (rdev->rlc.save_restore_obj == NULL) { /* save restore block */
r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, if (rdev->rlc.save_restore_obj == NULL) {
RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj); r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj);
if (r) {
dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
return r;
}
}
r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
if (unlikely(r != 0)) {
sumo_rlc_fini(rdev);
return r;
}
r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
&rdev->rlc.save_restore_gpu_addr);
if (r) { if (r) {
dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); radeon_bo_unreserve(rdev->rlc.save_restore_obj);
dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
sumo_rlc_fini(rdev);
return r; return r;
} }
}
r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
if (unlikely(r != 0)) { if (r) {
sumo_rlc_fini(rdev); dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
return r; sumo_rlc_fini(rdev);
} return r;
r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, }
&rdev->rlc.save_restore_gpu_addr); /* write the sr buffer */
if (r) { dst_ptr = rdev->rlc.sr_ptr;
/* format:
* dw0: (reg2 << 16) | reg1
* dw1: reg1 save space
* dw2: reg2 save space
*/
for (i = 0; i < dws; i++) {
data = src_ptr[i] >> 2;
i++;
if (i < dws)
data |= (src_ptr[i] >> 2) << 16;
j = (((i - 1) * 3) / 2);
dst_ptr[j] = data;
}
j = ((i * 3) / 2);
dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
radeon_bo_kunmap(rdev->rlc.save_restore_obj);
radeon_bo_unreserve(rdev->rlc.save_restore_obj); radeon_bo_unreserve(rdev->rlc.save_restore_obj);
dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
sumo_rlc_fini(rdev);
return r;
}
r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
if (r) {
dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
sumo_rlc_fini(rdev);
return r;
}
/* write the sr buffer */
dst_ptr = rdev->rlc.sr_ptr;
/* format:
* dw0: (reg2 << 16) | reg1
* dw1: reg1 save space
* dw2: reg2 save space
*/
for (i = 0; i < dws; i++) {
data = src_ptr[i] >> 2;
i++;
if (i < dws)
data |= (src_ptr[i] >> 2) << 16;
j = (((i - 1) * 3) / 2);
dst_ptr[j] = data;
} }
j = ((i * 3) / 2);
dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
radeon_bo_kunmap(rdev->rlc.save_restore_obj);
radeon_bo_unreserve(rdev->rlc.save_restore_obj);
/* clear state block */ if (cs_data) {
reg_list_num = 0; /* clear state block */
dws = 0; reg_list_num = 0;
for (i = 0; cs_data[i].section != NULL; i++) { dws = 0;
for (j = 0; cs_data[i].section[j].extent != NULL; j++) { for (i = 0; cs_data[i].section != NULL; i++) {
reg_list_num++; for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
dws += cs_data[i].section[j].reg_count; reg_list_num++;
dws += cs_data[i].section[j].reg_count;
}
} }
} reg_list_blk_index = (3 * reg_list_num + 2);
reg_list_blk_index = (3 * reg_list_num + 2); dws += reg_list_blk_index;
dws += reg_list_blk_index;
if (rdev->rlc.clear_state_obj == NULL) { if (rdev->rlc.clear_state_obj == NULL) {
r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj); RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
if (r) {
dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
sumo_rlc_fini(rdev);
return r;
}
}
r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
if (unlikely(r != 0)) {
sumo_rlc_fini(rdev);
return r;
}
r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
&rdev->rlc.clear_state_gpu_addr);
if (r) { if (r) {
dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); radeon_bo_unreserve(rdev->rlc.clear_state_obj);
dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
sumo_rlc_fini(rdev); sumo_rlc_fini(rdev);
return r; return r;
} }
}
r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
if (unlikely(r != 0)) {
sumo_rlc_fini(rdev);
return r;
}
r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
&rdev->rlc.clear_state_gpu_addr);
if (r) {
radeon_bo_unreserve(rdev->rlc.clear_state_obj); r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); if (r) {
sumo_rlc_fini(rdev); dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
return r; sumo_rlc_fini(rdev);
} return r;
r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr); }
if (r) { /* set up the cs buffer */
dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r); dst_ptr = rdev->rlc.cs_ptr;
sumo_rlc_fini(rdev); reg_list_hdr_blk_index = 0;
return r; reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
} data = upper_32_bits(reg_list_mc_addr);
/* set up the cs buffer */ dst_ptr[reg_list_hdr_blk_index] = data;
dst_ptr = rdev->rlc.cs_ptr; reg_list_hdr_blk_index++;
reg_list_hdr_blk_index = 0; for (i = 0; cs_data[i].section != NULL; i++) {
reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
data = upper_32_bits(reg_list_mc_addr); reg_num = cs_data[i].section[j].reg_count;
dst_ptr[reg_list_hdr_blk_index] = data; data = reg_list_mc_addr & 0xffffffff;
reg_list_hdr_blk_index++; dst_ptr[reg_list_hdr_blk_index] = data;
for (i = 0; cs_data[i].section != NULL; i++) { reg_list_hdr_blk_index++;
for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
reg_num = cs_data[i].section[j].reg_count; data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
data = reg_list_mc_addr & 0xffffffff; dst_ptr[reg_list_hdr_blk_index] = data;
dst_ptr[reg_list_hdr_blk_index] = data; reg_list_hdr_blk_index++;
reg_list_hdr_blk_index++;
data = 0x08000000 | (reg_num * 4);
data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff; dst_ptr[reg_list_hdr_blk_index] = data;
dst_ptr[reg_list_hdr_blk_index] = data; reg_list_hdr_blk_index++;
reg_list_hdr_blk_index++;
for (k = 0; k < reg_num; k++) {
data = 0x08000000 | (reg_num * 4); data = cs_data[i].section[j].extent[k];
dst_ptr[reg_list_hdr_blk_index] = data; dst_ptr[reg_list_blk_index + k] = data;
reg_list_hdr_blk_index++; }
reg_list_mc_addr += reg_num * 4;
for (k = 0; k < reg_num; k++) { reg_list_blk_index += reg_num;
data = cs_data[i].section[j].extent[k];
dst_ptr[reg_list_blk_index + k] = data;
} }
reg_list_mc_addr += reg_num * 4;
reg_list_blk_index += reg_num;
} }
} dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
radeon_bo_kunmap(rdev->rlc.clear_state_obj); radeon_bo_kunmap(rdev->rlc.clear_state_obj);
radeon_bo_unreserve(rdev->rlc.clear_state_obj); radeon_bo_unreserve(rdev->rlc.clear_state_obj);
}
return 0; return 0;
} }
......
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