Commit 143418d0 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc fixes from Benjamin Herrenschmidt:
 "This contains a couple more fixes for the system.h disintegration, a
  trivial section mismatch fix, a couple of patches from akpm that I
  didn't quite get he expected me to pickup, and a few more trivialities
  form Kumar that he appear to have forgotten to send me in the previous
  batch."

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc/eeh: Fix use of set_current_state() in eeh event handling set_current_state() wart
  powerpc/eeh: Remove eeh_event_handler()->daemonize()
  powerpc/kvm: Fallout from system.h disintegration
  powerpc: Fix fallout from system.h split up
  powerpc: Mark const init data with __initconst instead of __initdata
  powerpc/qe: Update the SNUM table for MPC8569 Rev2.0
  powerpc/dts: Removed fsl,msi property from dts.
  powerpc/epapr: add "memory" as a clobber to all hypercalls
  powerpc/85xx: Enable I2C_CHARDEV and I2C_MPC options in defconfigs
  powerpc/85xx: add the P1020UTM-PC DTS support
  powerpc/85xx: add the P1020MBG-PC DTS support
  powerpc/8xxx: remove 85xx/86xx restrictions from fsl_guts.h
parents deb74f5c 9b218f63
/*
* P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 128KB for DTB Image */
reg = <0x0 0x00020000>;
label = "NOR DTB Image";
};
partition@20000 {
/* 3.875 MB for Linux Kernel Image */
reg = <0x00020000 0x003e0000>;
label = "NOR Linux Kernel Image";
};
partition@400000 {
/* 58MB for Root file System */
reg = <0x00400000 0x03a00000>;
label = "NOR Root File System";
};
partition@3e00000 {
/* This location must not be altered */
/* 1M for Vitesse 7385 Switch firmware */
reg = <0x3e00000 0x00100000>;
label = "NOR Vitesse-7385 Firmware";
read-only;
};
partition@3f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x03f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
L2switch@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "vitesse-7385";
reg = <0x2 0x0 0x20000>;
};
};
&soc {
i2c@3000 {
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
usb@22000 {
phy_type = "ulpi";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
*/
usb@23000 {
status = "disabled";
phy_type = "ulpi";
};
};
/*
* P1020 MBG-PC Device Tree Source (32-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020MBG-PC";
compatible = "fsl,P1020MBG-PC";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0x0 0xffe05000 0x0 0x1000>;
/* NOR and L2 switch */
ranges = <0x0 0x0 0x0 0xec000000 0x04000000
0x1 0x0 0x0 0xffa00000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1020mbg-pc.dtsi"
/include/ "fsl/p1020si-post.dtsi"
/*
* P1020 MBG-PC Device Tree Source (36-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020MBG-PC";
compatible = "fsl,P1020MBG-PC";
memory {
device_type = "memory";
};
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0x0 0x1000>;
/* NOR and L2 switch */
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
0x1 0x0 0xf 0xffa00000 0x00040000
0x2 0x0 0xf 0xffb00000 0x00020000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1020mbg-pc.dtsi"
/include/ "fsl/p1020si-post.dtsi"
/*
* P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 256KB for DTB Image */
reg = <0x0 0x00040000>;
label = "NOR DTB Image";
};
partition@40000 {
/* 3.75 MB for Linux Kernel Image */
reg = <0x00040000 0x003c0000>;
label = "NOR Linux Kernel Image";
};
partition@400000 {
/* 27MB for Root file System */
reg = <0x00400000 0x01b00000>;
label = "NOR Root File System";
};
partition@1f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x01f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
};
&soc {
i2c@3000 {
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
phy2: ethernet-phy@2 {
interrupts = <1 1 0 0>;
reg = <0x2>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
usb@22000 {
phy_type = "ulpi";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
*/
usb@23000 {
status = "disabled";
phy_type = "ulpi";
};
};
/*
* P1020 UTM-PC Device Tree Source (32-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020UTM-PC";
compatible = "fsl,P1020UTM-PC";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0x0 0xffe05000 0x0 0x1000>;
/* NOR */
ranges = <0x0 0x0 0x0 0xec000000 0x02000000
0x1 0x0 0x0 0xffa00000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1020utm-pc.dtsi"
/include/ "fsl/p1020si-post.dtsi"
/*
* P1020 UTM-PC Device Tree Source (36-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020UTM-PC";
compatible = "fsl,P1020UTM-PC";
memory {
device_type = "memory";
};
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0x0 0x1000>;
/* NOR */
ranges = <0x0 0x0 0xf 0xec000000 0x02000000
0x1 0x0 0xf 0xffa00000 0x00040000
0x2 0x0 0xf 0xffb00000 0x00020000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1020utm-pc.dtsi"
/include/ "fsl/p1020si-post.dtsi"
...@@ -135,7 +135,6 @@ pci0: pcie@ffe200000 { ...@@ -135,7 +135,6 @@ pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>; reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
fsl,msi = <&msi0>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -151,7 +150,6 @@ pci1: pcie@ffe201000 { ...@@ -151,7 +150,6 @@ pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>; reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
fsl,msi = <&msi1>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -167,7 +165,6 @@ pci2: pcie@ffe202000 { ...@@ -167,7 +165,6 @@ pci2: pcie@ffe202000 {
reg = <0xf 0xfe202000 0 0x1000>; reg = <0xf 0xfe202000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
fsl,msi = <&msi2>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
......
...@@ -173,7 +173,6 @@ pci0: pcie@ffe200000 { ...@@ -173,7 +173,6 @@ pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>; reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
fsl,msi = <&msi0>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -189,7 +188,6 @@ pci1: pcie@ffe201000 { ...@@ -189,7 +188,6 @@ pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>; reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
fsl,msi = <&msi1>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -205,7 +203,6 @@ pci2: pcie@ffe202000 { ...@@ -205,7 +203,6 @@ pci2: pcie@ffe202000 {
reg = <0xf 0xfe202000 0 0x1000>; reg = <0xf 0xfe202000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
fsl,msi = <&msi2>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -221,7 +218,6 @@ pci3: pcie@ffe203000 { ...@@ -221,7 +218,6 @@ pci3: pcie@ffe203000 {
reg = <0xf 0xfe203000 0 0x1000>; reg = <0xf 0xfe203000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
fsl,msi = <&msi2>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
......
...@@ -212,7 +212,6 @@ pci0: pcie@ffe200000 { ...@@ -212,7 +212,6 @@ pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>; reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
fsl,msi = <&msi0>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -228,7 +227,6 @@ pci1: pcie@ffe201000 { ...@@ -228,7 +227,6 @@ pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>; reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
fsl,msi = <&msi1>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
......
...@@ -141,7 +141,6 @@ pci0: pcie@ffe200000 { ...@@ -141,7 +141,6 @@ pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>; reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
fsl,msi = <&msi0>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -157,7 +156,6 @@ pci1: pcie@ffe201000 { ...@@ -157,7 +156,6 @@ pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>; reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
fsl,msi = <&msi1>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -173,7 +171,6 @@ pci2: pcie@ffe202000 { ...@@ -173,7 +171,6 @@ pci2: pcie@ffe202000 {
reg = <0xf 0xfe202000 0 0x1000>; reg = <0xf 0xfe202000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
fsl,msi = <&msi2>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
......
...@@ -173,7 +173,6 @@ pci0: pcie@ffe200000 { ...@@ -173,7 +173,6 @@ pci0: pcie@ffe200000 {
reg = <0xf 0xfe200000 0 0x1000>; reg = <0xf 0xfe200000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
fsl,msi = <&msi0>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -189,7 +188,6 @@ pci1: pcie@ffe201000 { ...@@ -189,7 +188,6 @@ pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>; reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
fsl,msi = <&msi1>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -205,7 +203,6 @@ pci2: pcie@ffe202000 { ...@@ -205,7 +203,6 @@ pci2: pcie@ffe202000 {
reg = <0xf 0xfe202000 0 0x1000>; reg = <0xf 0xfe202000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
fsl,msi = <&msi2>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
...@@ -221,7 +218,6 @@ pci3: pcie@ffe203000 { ...@@ -221,7 +218,6 @@ pci3: pcie@ffe203000 {
reg = <0xf 0xfe203000 0 0x1000>; reg = <0xf 0xfe203000 0 0x1000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
fsl,msi = <&msi2>;
pcie@0 { pcie@0 {
ranges = <0x02000000 0 0xe0000000 ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000 0x02000000 0 0xe0000000
......
...@@ -116,6 +116,7 @@ CONFIG_SERIAL_8250_RSA=y ...@@ -116,6 +116,7 @@ CONFIG_SERIAL_8250_RSA=y
CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM=y
CONFIG_NVRAM=y CONFIG_NVRAM=y
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y CONFIG_I2C_MPC=y
CONFIG_SPI=y CONFIG_SPI=y
CONFIG_SPI_GPIO=y CONFIG_SPI_GPIO=y
......
...@@ -71,6 +71,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y ...@@ -71,6 +71,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_RSA=y
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
# CONFIG_HWMON is not set # CONFIG_HWMON is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_VIDEO_OUTPUT_CONTROL=y
# CONFIG_HID_SUPPORT is not set # CONFIG_HID_SUPPORT is not set
......
...@@ -117,6 +117,7 @@ CONFIG_SERIAL_8250_RSA=y ...@@ -117,6 +117,7 @@ CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_QE=m CONFIG_SERIAL_QE=m
CONFIG_NVRAM=y CONFIG_NVRAM=y
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_CPM=m CONFIG_I2C_CPM=m
CONFIG_I2C_MPC=y CONFIG_I2C_MPC=y
CONFIG_SPI=y CONFIG_SPI=y
......
...@@ -119,6 +119,7 @@ CONFIG_SERIAL_8250_RSA=y ...@@ -119,6 +119,7 @@ CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_QE=m CONFIG_SERIAL_QE=m
CONFIG_NVRAM=y CONFIG_NVRAM=y
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_CPM=m CONFIG_I2C_CPM=m
CONFIG_I2C_MPC=y CONFIG_I2C_MPC=y
CONFIG_SPI=y CONFIG_SPI=y
......
...@@ -134,10 +134,15 @@ ...@@ -134,10 +134,15 @@
* whether they will be clobbered. * whether they will be clobbered.
* *
* Note that r11 can be used as an output parameter. * Note that r11 can be used as an output parameter.
*
* The "memory" clobber is only necessary for hcalls where the Hypervisor
* will read or write guest memory. However, we add it to all hcalls because
* the impact is minimal, and we want to ensure that it's present for the
* hcalls that need it.
*/ */
/* List of common clobbered registers. Do not use this macro. */ /* List of common clobbered registers. Do not use this macro. */
#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc" #define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory"
#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS #define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS
#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10" #define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10"
......
...@@ -16,15 +16,6 @@ ...@@ -16,15 +16,6 @@
#define __ASM_POWERPC_FSL_GUTS_H__ #define __ASM_POWERPC_FSL_GUTS_H__
#ifdef __KERNEL__ #ifdef __KERNEL__
/*
* These #ifdefs are safe because it's not possible to build a kernel that
* runs on e500 and e600 cores.
*/
#if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx)
#error Only 85xx and 86xx SOCs are supported
#endif
/** /**
* Global Utility Registers. * Global Utility Registers.
* *
...@@ -36,11 +27,7 @@ ...@@ -36,11 +27,7 @@
* different names. In these cases, one name is chosen to avoid extraneous * different names. In these cases, one name is chosen to avoid extraneous
* #ifdefs. * #ifdefs.
*/ */
#ifdef CONFIG_PPC_85xx struct ccsr_guts {
struct ccsr_guts_85xx {
#else
struct ccsr_guts_86xx {
#endif
__be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
__be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
__be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
...@@ -77,11 +64,8 @@ struct ccsr_guts_86xx { ...@@ -77,11 +64,8 @@ struct ccsr_guts_86xx {
u8 res0a8[0xb0 - 0xa8]; u8 res0a8[0xb0 - 0xa8];
__be32 rstcr; /* 0x.00b0 - Reset Control Register */ __be32 rstcr; /* 0x.00b0 - Reset Control Register */
u8 res0b4[0xc0 - 0xb4]; u8 res0b4[0xc0 - 0xb4];
#ifdef CONFIG_PPC_85xx __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register */ Called 'elbcvselcr' on 86xx SOCs */
#else
__be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
#endif
u8 res0c4[0x224 - 0xc4]; u8 res0c4[0x224 - 0xc4];
__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
...@@ -136,7 +120,7 @@ struct ccsr_guts_86xx { ...@@ -136,7 +120,7 @@ struct ccsr_guts_86xx {
* ch: The channel on the DMA controller (0, 1, 2, or 3) * ch: The channel on the DMA controller (0, 1, 2, or 3)
* device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
*/ */
static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts, static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int device) unsigned int co, unsigned int ch, unsigned int device)
{ {
unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
...@@ -172,7 +156,7 @@ static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts, ...@@ -172,7 +156,7 @@ static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
* ch: The channel on the DMA controller (0, 1, 2, or 3) * ch: The channel on the DMA controller (0, 1, 2, or 3)
* value: the new value for the bit (0 or 1) * value: the new value for the bit (0 or 1)
*/ */
static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts, static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int value) unsigned int co, unsigned int ch, unsigned int value)
{ {
if ((ch == 0) || (ch == 3)) { if ((ch == 0) || (ch == 3)) {
......
...@@ -40,6 +40,8 @@ ...@@ -40,6 +40,8 @@
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/rtas.h> #include <asm/rtas.h>
#include <asm/fadump.h> #include <asm/fadump.h>
#include <asm/debug.h>
#include <asm/setup.h>
static struct fw_dump fw_dump; static struct fw_dump fw_dump;
static struct fadump_mem_struct fdm; static struct fadump_mem_struct fdm;
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <asm/current.h> #include <asm/current.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/debug.h>
/* /*
* This table contains the mapping between PowerPC hardware trap types, and * This table contains the mapping between PowerPC hardware trap types, and
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <asm/disassemble.h> #include <asm/disassemble.h>
#include <asm/kvm_book3s.h> #include <asm/kvm_book3s.h>
#include <asm/reg.h> #include <asm/reg.h>
#include <asm/switch_to.h>
#define OP_19_XOP_RFID 18 #define OP_19_XOP_RFID 18
#define OP_19_XOP_RFI 50 #define OP_19_XOP_RFI 50
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <asm/kvm_fpu.h> #include <asm/kvm_fpu.h>
#include <asm/reg.h> #include <asm/reg.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/switch_to.h>
#include <linux/vmalloc.h> #include <linux/vmalloc.h>
/* #define DEBUG */ /* #define DEBUG */
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <asm/kvm_ppc.h> #include <asm/kvm_ppc.h>
#include <asm/kvm_book3s.h> #include <asm/kvm_book3s.h>
#include <asm/mmu_context.h> #include <asm/mmu_context.h>
#include <asm/switch_to.h>
#include <linux/gfp.h> #include <linux/gfp.h>
#include <linux/sched.h> #include <linux/sched.h>
#include <linux/vmalloc.h> #include <linux/vmalloc.h>
......
...@@ -93,7 +93,7 @@ struct mpc52xx_pci { ...@@ -93,7 +93,7 @@ struct mpc52xx_pci {
}; };
/* MPC5200 device tree match tables */ /* MPC5200 device tree match tables */
const struct of_device_id mpc52xx_pci_ids[] __initdata = { const struct of_device_id mpc52xx_pci_ids[] __initconst = {
{ .type = "pci", .compatible = "fsl,mpc5200-pci", }, { .type = "pci", .compatible = "fsl,mpc5200-pci", },
{ .type = "pci", .compatible = "mpc5200-pci", }, { .type = "pci", .compatible = "mpc5200-pci", },
{} {}
......
...@@ -270,7 +270,7 @@ static void __init mpc85xx_mds_qe_init(void) ...@@ -270,7 +270,7 @@ static void __init mpc85xx_mds_qe_init(void)
if (machine_is(p1021_mds)) { if (machine_is(p1021_mds)) {
struct ccsr_guts_85xx __iomem *guts; struct ccsr_guts __iomem *guts;
np = of_find_node_by_name(NULL, "global-utilities"); np = of_find_node_by_name(NULL, "global-utilities");
if (np) { if (np) {
......
...@@ -127,7 +127,7 @@ static void __init mpc85xx_rdb_setup_arch(void) ...@@ -127,7 +127,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) { if (machine_is(p1025_rdb)) {
struct ccsr_guts_85xx __iomem *guts; struct ccsr_guts __iomem *guts;
np = of_find_node_by_name(NULL, "global-utilities"); np = of_find_node_by_name(NULL, "global-utilities");
if (np) { if (np) {
......
...@@ -150,7 +150,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) ...@@ -150,7 +150,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
{ {
struct device_node *guts_node; struct device_node *guts_node;
struct device_node *indirect_node = NULL; struct device_node *indirect_node = NULL;
struct ccsr_guts_85xx __iomem *guts; struct ccsr_guts __iomem *guts;
u8 __iomem *lbc_lcs0_ba = NULL; u8 __iomem *lbc_lcs0_ba = NULL;
u8 __iomem *lbc_lcs1_ba = NULL; u8 __iomem *lbc_lcs1_ba = NULL;
u8 b; u8 b;
...@@ -269,7 +269,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) ...@@ -269,7 +269,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
void p1022ds_set_pixel_clock(unsigned int pixclock) void p1022ds_set_pixel_clock(unsigned int pixclock)
{ {
struct device_node *guts_np = NULL; struct device_node *guts_np = NULL;
struct ccsr_guts_85xx __iomem *guts; struct ccsr_guts __iomem *guts;
unsigned long freq; unsigned long freq;
u64 temp; u64 temp;
u32 pxclk; u32 pxclk;
......
...@@ -225,7 +225,7 @@ void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port) ...@@ -225,7 +225,7 @@ void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
{ {
struct device_node *guts_np = NULL; struct device_node *guts_np = NULL;
struct ccsr_guts_86xx __iomem *guts; struct ccsr_guts __iomem *guts;
unsigned long freq; unsigned long freq;
u64 temp; u64 temp;
u32 pxclk; u32 pxclk;
......
...@@ -61,7 +61,7 @@ static void qpace_progress(char *s, unsigned short hex) ...@@ -61,7 +61,7 @@ static void qpace_progress(char *s, unsigned short hex)
printk("*** %04x : %s\n", hex, s ? s : ""); printk("*** %04x : %s\n", hex, s ? s : "");
} }
static const struct of_device_id qpace_bus_ids[] __initdata = { static const struct of_device_id qpace_bus_ids[] __initconst = {
{ .type = "soc", }, { .type = "soc", },
{ .compatible = "soc", }, { .compatible = "soc", },
{ .type = "spider", }, { .type = "spider", },
......
...@@ -140,7 +140,7 @@ static int __devinit cell_setup_phb(struct pci_controller *phb) ...@@ -140,7 +140,7 @@ static int __devinit cell_setup_phb(struct pci_controller *phb)
return 0; return 0;
} }
static const struct of_device_id cell_bus_ids[] __initdata = { static const struct of_device_id cell_bus_ids[] __initconst = {
{ .type = "soc", }, { .type = "soc", },
{ .compatible = "soc", }, { .compatible = "soc", },
{ .type = "spider", }, { .type = "spider", },
......
...@@ -59,8 +59,7 @@ static int eeh_event_handler(void * dummy) ...@@ -59,8 +59,7 @@ static int eeh_event_handler(void * dummy)
struct eeh_event *event; struct eeh_event *event;
struct eeh_dev *edev; struct eeh_dev *edev;
daemonize("eehd"); set_task_comm(current, "eehd");
set_current_state(TASK_INTERRUPTIBLE);
spin_lock_irqsave(&eeh_eventlist_lock, flags); spin_lock_irqsave(&eeh_eventlist_lock, flags);
event = NULL; event = NULL;
...@@ -83,6 +82,7 @@ static int eeh_event_handler(void * dummy) ...@@ -83,6 +82,7 @@ static int eeh_event_handler(void * dummy)
printk(KERN_INFO "EEH: Detected PCI bus error on device %s\n", printk(KERN_INFO "EEH: Detected PCI bus error on device %s\n",
eeh_pci_name(edev->pdev)); eeh_pci_name(edev->pdev));
set_current_state(TASK_INTERRUPTIBLE); /* Don't add to load average */
edev = handle_eeh_events(event); edev = handle_eeh_events(event);
eeh_clear_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING); eeh_clear_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
......
/* /*
* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. * Copyright (C) 2006-2010 Freescale Semicondutor, Inc. All rights reserved.
* *
* Authors: Shlomi Gridish <gridish@freescale.com> * Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com> * Li Yang <leoli@freescale.com>
...@@ -266,7 +266,19 @@ EXPORT_SYMBOL(qe_clock_source); ...@@ -266,7 +266,19 @@ EXPORT_SYMBOL(qe_clock_source);
static void qe_snums_init(void) static void qe_snums_init(void)
{ {
int i; int i;
static const u8 snum_init[] = { static const u8 snum_init_76[] = {
0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
0xF4, 0xF5, 0xFC, 0xFD,
};
static const u8 snum_init_46[] = {
0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9, 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
...@@ -274,9 +286,15 @@ static void qe_snums_init(void) ...@@ -274,9 +286,15 @@ static void qe_snums_init(void)
0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
0x68, 0x69, 0x78, 0x79, 0x80, 0x81, 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
}; };
static const u8 *snum_init;
qe_num_of_snum = qe_get_num_of_snums(); qe_num_of_snum = qe_get_num_of_snums();
if (qe_num_of_snum == 76)
snum_init = snum_init_76;
else
snum_init = snum_init_46;
for (i = 0; i < qe_num_of_snum; i++) { for (i = 0; i < qe_num_of_snum; i++) {
snums[i].num = snum_init[i]; snums[i].num = snum_init[i];
snums[i].state = QE_SNUM_STATE_FREE; snums[i].state = QE_SNUM_STATE_FREE;
......
...@@ -3945,6 +3945,8 @@ static int ucc_geth_probe(struct platform_device* ofdev) ...@@ -3945,6 +3945,8 @@ static int ucc_geth_probe(struct platform_device* ofdev)
} }
if (max_speed == SPEED_1000) { if (max_speed == SPEED_1000) {
unsigned int snums = qe_get_num_of_snums();
/* configure muram FIFOs for gigabit operation */ /* configure muram FIFOs for gigabit operation */
ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
...@@ -3954,11 +3956,11 @@ static int ucc_geth_probe(struct platform_device* ofdev) ...@@ -3954,11 +3956,11 @@ static int ucc_geth_probe(struct platform_device* ofdev)
ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
/* If QE's snum number is 46 which means we need to support /* If QE's snum number is 46/76 which means we need to support
* 4 UECs at 1000Base-T simultaneously, we need to allocate * 4 UECs at 1000Base-T simultaneously, we need to allocate
* more Threads to Rx. * more Threads to Rx.
*/ */
if (qe_get_num_of_snums() == 46) if ((snums == 76) || (snums == 46))
ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
else else
ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
......
...@@ -58,9 +58,9 @@ static int mpc8610_hpcd_machine_probe(struct snd_soc_card *card) ...@@ -58,9 +58,9 @@ static int mpc8610_hpcd_machine_probe(struct snd_soc_card *card)
{ {
struct mpc8610_hpcd_data *machine_data = struct mpc8610_hpcd_data *machine_data =
container_of(card, struct mpc8610_hpcd_data, card); container_of(card, struct mpc8610_hpcd_data, card);
struct ccsr_guts_86xx __iomem *guts; struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts_86xx)); guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) { if (!guts) {
dev_err(card->dev, "could not map global utilities\n"); dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM; return -ENOMEM;
...@@ -142,9 +142,9 @@ static int mpc8610_hpcd_machine_remove(struct snd_soc_card *card) ...@@ -142,9 +142,9 @@ static int mpc8610_hpcd_machine_remove(struct snd_soc_card *card)
{ {
struct mpc8610_hpcd_data *machine_data = struct mpc8610_hpcd_data *machine_data =
container_of(card, struct mpc8610_hpcd_data, card); container_of(card, struct mpc8610_hpcd_data, card);
struct ccsr_guts_86xx __iomem *guts; struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts_86xx)); guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) { if (!guts) {
dev_err(card->dev, "could not map global utilities\n"); dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM; return -ENOMEM;
......
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
* ch: The channel on the DMA controller (0, 1, 2, or 3) * ch: The channel on the DMA controller (0, 1, 2, or 3)
* device: The device to set as the target (CCSR_GUTS_DMUXCR_xxx) * device: The device to set as the target (CCSR_GUTS_DMUXCR_xxx)
*/ */
static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts, static inline void guts_set_dmuxcr(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int device) unsigned int co, unsigned int ch, unsigned int device)
{ {
unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
...@@ -90,9 +90,9 @@ static int p1022_ds_machine_probe(struct snd_soc_card *card) ...@@ -90,9 +90,9 @@ static int p1022_ds_machine_probe(struct snd_soc_card *card)
{ {
struct machine_data *mdata = struct machine_data *mdata =
container_of(card, struct machine_data, card); container_of(card, struct machine_data, card);
struct ccsr_guts_85xx __iomem *guts; struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts_85xx)); guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) { if (!guts) {
dev_err(card->dev, "could not map global utilities\n"); dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM; return -ENOMEM;
...@@ -164,9 +164,9 @@ static int p1022_ds_machine_remove(struct snd_soc_card *card) ...@@ -164,9 +164,9 @@ static int p1022_ds_machine_remove(struct snd_soc_card *card)
{ {
struct machine_data *mdata = struct machine_data *mdata =
container_of(card, struct machine_data, card); container_of(card, struct machine_data, card);
struct ccsr_guts_85xx __iomem *guts; struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts_85xx)); guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) { if (!guts) {
dev_err(card->dev, "could not map global utilities\n"); dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM; return -ENOMEM;
......
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