Commit 14b596c9 authored by Kristina Martšenko's avatar Kristina Martšenko Committed by Greg Kroah-Hartman

staging: cxt1e1: remove driver

Remove the driver as it hasn't been cleaned up and it doesn't look like
anyone is going to work on it anymore. This can be reverted if someone
wants to work to fix the remaining issues the driver has.
Signed-off-by: default avatarKristina Martšenko <kristina.martsenko@gmail.com>
Cc: Bob Beers <bob.beers@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 19b1e769
...@@ -72,8 +72,6 @@ source "drivers/staging/sep/Kconfig" ...@@ -72,8 +72,6 @@ source "drivers/staging/sep/Kconfig"
source "drivers/staging/iio/Kconfig" source "drivers/staging/iio/Kconfig"
source "drivers/staging/cxt1e1/Kconfig"
source "drivers/staging/xgifb/Kconfig" source "drivers/staging/xgifb/Kconfig"
source "drivers/staging/tidspbridge/Kconfig" source "drivers/staging/tidspbridge/Kconfig"
......
...@@ -30,7 +30,6 @@ obj-$(CONFIG_VT6656) += vt6656/ ...@@ -30,7 +30,6 @@ obj-$(CONFIG_VT6656) += vt6656/
obj-$(CONFIG_VME_BUS) += vme/ obj-$(CONFIG_VME_BUS) += vme/
obj-$(CONFIG_DX_SEP) += sep/ obj-$(CONFIG_DX_SEP) += sep/
obj-$(CONFIG_IIO) += iio/ obj-$(CONFIG_IIO) += iio/
obj-$(CONFIG_CXT1E1) += cxt1e1/
obj-$(CONFIG_FB_XGI) += xgifb/ obj-$(CONFIG_FB_XGI) += xgifb/
obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/ obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/ obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
......
config CXT1E1
tristate "SBE wanPMC-C[421]E1T1 hardware support"
depends on HDLC && PCI
---help---
This driver supports the SBE wanPMC-CxT1E1 1, 2 and 4 port T3
channelized stream WAN adapter card which contains a HDLC/Transparent
mode controller.
If you want to compile this driver as a module say M here.
The module will be called 'cxt1e1'.
If unsure, say N.
config SBE_PMCC4_NCOMM
bool "SBE PMCC4 NCOMM support"
depends on CXT1E1
---help---
SBE supplies optional support for NCOMM products.
If you have purchased this optional support you must say Y
here to allow the driver to operate with the NCOMM product.
obj-$(CONFIG_CXT1E1) += cxt1e1.o
ccflags-y := -DSBE_PMCC4_ENABLE
ccflags-y += -DSBE_ISR_TASKLET
cxt1e1-y := \
musycc.o \
pmcc4_drv.o \
comet.o \
linux.o \
functions.o \
hwprobe.o \
pmc93x6_eeprom.o \
sbecrc.o \
comet_tables.o \
sbeid.o
cxt1e1-$(CONFIG_PROC_FS) += sbeproc.o
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#ifndef _INC_COMET_TBLS_H_
#define _INC_COMET_TBLS_H_
/*-----------------------------------------------------------------------------
* comet_tables.h - Waveform Tables for the PM4351 'COMET'
*
* Copyright (C) 2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* For further information, contact via email: support@sbei.com
* SBE, Inc. San Ramon, California U.S.A.
*-----------------------------------------------------------------------------
*/
/*****************************************************************************
*
* Array names:
*
* TWVLongHaul0DB
* TWVLongHaul7_5DB
* TWVLongHaul15DB
* TWVLongHaul22_5DB
* TWVShortHaul0
* TWVShortHaul1
* TWVShortHaul2
* TWVShortHaul3
* TWVShortHaul4
* TWVShortHaul5
* TWV_E1_120Ohm
* TWV_E1_75Ohm <not supported>
* T1_Equalizer
* E1_Equalizer
*
*****************************************************************************/
extern u_int8_t TWVLongHaul0DB[25][5]; /* T1 Long Haul 0 DB */
extern u_int8_t TWVLongHaul7_5DB[25][5]; /* T1 Long Haul 7.5 DB */
extern u_int8_t TWVLongHaul15DB[25][5]; /* T1 Long Haul 15 DB */
extern u_int8_t TWVLongHaul22_5DB[25][5]; /* T1 Long Haul 22.5 DB */
extern u_int8_t TWVShortHaul0[25][5]; /* T1 Short Haul 0-110 ft */
extern u_int8_t TWVShortHaul1[25][5]; /* T1 Short Haul 110-220 ft */
extern u_int8_t TWVShortHaul2[25][5]; /* T1 Short Haul 220-330 ft */
extern u_int8_t TWVShortHaul3[25][5]; /* T1 Short Haul 330-440 ft */
extern u_int8_t TWVShortHaul4[25][5]; /* T1 Short Haul 440-550 ft */
extern u_int8_t TWVShortHaul5[25][5]; /* T1 Short Haul 550-660 ft */
extern u_int8_t TWV_E1_75Ohm[25][5]; /* E1 75 Ohm */
extern u_int8_t TWV_E1_120Ohm[25][5]; /* E1 120 Ohm */
extern u_int32_t T1_Equalizer[256]; /* T1 Receiver Equalizer */
extern u_int32_t E1_Equalizer[256]; /* E1 Receiver Equalizer */
#endif /* _INC_COMET_TBLS_H_ */
/* Copyright (C) 2003-2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/slab.h>
#include <linux/io.h>
#include <asm/byteorder.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/hdlc.h>
#include "pmcc4_sysdep.h"
#include "sbecom_inline_linux.h"
#include "libsbew.h"
#include "pmcc4.h"
#ifndef USE_MAX_INT_DELAY
static int dummy = 0;
#endif
extern int drvr_state;
#if 1
u_int32_t
pci_read_32(u_int32_t *p)
{
#ifdef FLOW_DEBUG
u_int32_t v;
FLUSH_PCI_READ();
v = le32_to_cpu(*p);
if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
return v;
#else
FLUSH_PCI_READ(); /* */
return le32_to_cpu(*p);
#endif
}
void
pci_write_32(u_int32_t *p, u_int32_t v)
{
#ifdef FLOW_DEBUG
if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
#endif
*p = cpu_to_le32 (v);
FLUSH_PCI_WRITE(); /* This routine is called from routines
* which do multiple register writes
* which themselves need flushing between
* writes in order to guarantee write
* ordering. It is less code-cumbersome
* to flush here-in then to investigate
* and code the many other register
* writing routines. */
}
#endif
void
pci_flush_write(ci_t *ci)
{
volatile u_int32_t v;
/* issue a PCI read to flush PCI write thru bridge */
v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
/*
* return nothing, this just reads PCI bridge interface to flush
* previously written data
*/
}
static void
watchdog_func(unsigned long arg)
{
struct watchdog *wd = (void *) arg;
if (drvr_state != SBE_DRVR_AVAILABLE) {
if (cxt1e1_log_level >= LOG_MONITOR)
pr_warning("%s: drvr not available (%x)\n",
__func__, drvr_state);
return;
}
schedule_work(&wd->work);
mod_timer(&wd->h, jiffies + wd->ticks);
}
int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *),
void *c, int usec)
{
wdp->func = f;
wdp->softc = c;
wdp->ticks = (HZ) * (usec / 1000) / 1000;
INIT_WORK(&wdp->work, (void *)f);
init_timer(&wdp->h);
{
ci_t *ci = (ci_t *) c;
wdp->h.data = (unsigned long) &ci->wd;
}
wdp->h.function = watchdog_func;
return 0;
}
void
OS_uwait(int usec, char *description)
{
int tmp;
if (usec >= 1000) {
mdelay(usec / 1000);
/* now delay residual */
tmp = (usec / 1000) * 1000; /* round */
tmp = usec - tmp; /* residual */
if (tmp) { /* wait on residual */
udelay(tmp);
}
} else {
udelay(usec);
}
}
/* dummy short delay routine called as a subroutine so that compiler
* does not optimize/remove its intent (a short delay)
*/
void
OS_uwait_dummy(void)
{
#ifndef USE_MAX_INT_DELAY
dummy++;
#else
udelay(1);
#endif
}
void
OS_sem_init(void *sem, int state)
{
switch (state) {
case SEM_TAKEN:
sema_init((struct semaphore *) sem, 0);
break;
case SEM_AVAILABLE:
sema_init((struct semaphore *) sem, 1);
break;
default: /* otherwise, set sem.count to state's
* value */
sema_init(sem, state);
break;
}
}
int
sd_line_is_ok(void *user)
{
struct net_device *ndev = (struct net_device *) user;
return netif_carrier_ok(ndev);
}
void
sd_line_is_up(void *user)
{
struct net_device *ndev = (struct net_device *) user;
netif_carrier_on(ndev);
return;
}
void
sd_line_is_down(void *user)
{
struct net_device *ndev = (struct net_device *) user;
netif_carrier_off(ndev);
return;
}
void
sd_disable_xmit(void *user)
{
struct net_device *dev = (struct net_device *) user;
netif_stop_queue(dev);
return;
}
void
sd_enable_xmit(void *user)
{
struct net_device *dev = (struct net_device *) user;
netif_wake_queue(dev);
return;
}
int
sd_queue_stopped(void *user)
{
struct net_device *ndev = (struct net_device *) user;
return netif_queue_stopped(ndev);
}
void sd_recv_consume(void *token, size_t len, void *user)
{
struct net_device *ndev = user;
struct sk_buff *skb = token;
skb->dev = ndev;
skb_put(skb, len);
skb->protocol = hdlc_type_trans(skb, ndev);
netif_rx(skb);
}
/**
** Read some reserved location w/in the COMET chip as a usable
** VMETRO trigger point or other trace marking event.
**/
#include "comet.h"
extern ci_t *CI; /* dummy pointer to board ZERO's data */
void
VMETRO_TRIGGER(ci_t *ci, int x)
{
struct s_comet_reg *comet;
volatile u_int32_t data;
comet = ci->port[0].cometbase; /* default to COMET # 0 */
switch (x) {
default:
case 0:
data = pci_read_32((u_int32_t *) &comet->__res24); /* 0x90 */
break;
case 1:
data = pci_read_32((u_int32_t *) &comet->__res25); /* 0x94 */
break;
case 2:
data = pci_read_32((u_int32_t *) &comet->__res26); /* 0x98 */
break;
case 3:
data = pci_read_32((u_int32_t *) &comet->__res27); /* 0x9C */
break;
case 4:
data = pci_read_32((u_int32_t *) &comet->__res88); /* 0x220 */
break;
case 5:
data = pci_read_32((u_int32_t *) &comet->__res89); /* 0x224 */
break;
case 6:
data = pci_read_32((u_int32_t *) &comet->__res8A); /* 0x228 */
break;
case 7:
data = pci_read_32((u_int32_t *) &comet->__res8B); /* 0x22C */
break;
case 8:
data = pci_read_32((u_int32_t *) &comet->__resA0); /* 0x280 */
break;
case 9:
data = pci_read_32((u_int32_t *) &comet->__resA1); /* 0x284 */
break;
case 10:
data = pci_read_32((u_int32_t *) &comet->__resA2); /* 0x288 */
break;
case 11:
data = pci_read_32((u_int32_t *) &comet->__resA3); /* 0x28C */
break;
case 12:
data = pci_read_32((u_int32_t *) &comet->__resA4); /* 0x290 */
break;
case 13:
data = pci_read_32((u_int32_t *) &comet->__resA5); /* 0x294 */
break;
case 14:
data = pci_read_32((u_int32_t *) &comet->__resA6); /* 0x298 */
break;
case 15:
data = pci_read_32((u_int32_t *) &comet->__resA7); /* 0x29C */
break;
case 16:
data = pci_read_32((u_int32_t *) &comet->__res74); /* 0x1D0 */
break;
case 17:
data = pci_read_32((u_int32_t *) &comet->__res75); /* 0x1D4 */
break;
case 18:
data = pci_read_32((u_int32_t *) &comet->__res76); /* 0x1D8 */
break;
case 19:
data = pci_read_32((u_int32_t *) &comet->__res77); /* 0x1DC */
break;
}
}
/*** End-of-File ***/
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#ifndef _INC_PMC93X6_EEPROM_H_
#define _INC_PMC93X6_EEPROM_H_
/*-----------------------------------------------------------------------------
* pmc93x6_eeprom.h -
*
* Copyright (C) 2002-2004 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* For further information, contact via email: support@sbei.com
* SBE, Inc. San Ramon, California U.S.A.
*-----------------------------------------------------------------------------
*/
#include <linux/types.h>
#ifdef __KERNEL__
#include "pmcc4_private.h"
void pmc_eeprom_read_buffer (long, long, char *, int);
void pmc_eeprom_write_buffer (long, long, char *, int);
void pmc_init_seeprom (u_int32_t, u_int32_t);
char pmc_verify_cksum (void *);
#endif /*** __KERNEL__ ***/
#endif
/*** End-of-File ***/
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