Commit 14c7c02d authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo

arm64: dts: imx8qxp: fix mbox-cells

Currently lsio_mu1 is used by Linux Kernel with mbox-cells as 2, but
actually mu0-4 could be used to communicate with SCU. So fix the
mbox-cells.
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Fixes: 3d91ba65 ("arm64: dts: imx: add imx8qxp support")
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ee4c12f4
...@@ -358,7 +358,7 @@ lsio_mu0: mailbox@5d1b0000 { ...@@ -358,7 +358,7 @@ lsio_mu0: mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>; reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>; #mbox-cells = <2>;
status = "disabled"; status = "disabled";
}; };
...@@ -373,7 +373,7 @@ lsio_mu3: mailbox@5d1e0000 { ...@@ -373,7 +373,7 @@ lsio_mu3: mailbox@5d1e0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1e0000 0x10000>; reg = <0x5d1e0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>; #mbox-cells = <2>;
status = "disabled"; status = "disabled";
}; };
...@@ -381,7 +381,7 @@ lsio_mu4: mailbox@5d1f0000 { ...@@ -381,7 +381,7 @@ lsio_mu4: mailbox@5d1f0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1f0000 0x10000>; reg = <0x5d1f0000 0x10000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>; #mbox-cells = <2>;
status = "disabled"; status = "disabled";
}; };
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment