drm/nouveau/nvif: replace pushbuf with vm in fermi/kepler gpfifo class args

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvif/class.h

@@ -354,9 +354,18 @@ struct nvif_control_pstate_user_v0 {
  ******************************************************************************/
 
 struct nv03_channel_dma_v0 {
+	__u8  version;
+	__u8  chid;
+	__u8  pad02[2];
+	__u32 offset;
+	__u64 pushbuf;
+};
+
+struct nv50_channel_dma_v0 {
 	__u8  version;
 	__u8  chid;
 	__u8  pad02[6];
+	__u64 vm;
 	__u64 pushbuf;
 	__u64 offset;
 };
@@ -374,6 +383,16 @@ struct nv50_channel_gpfifo_v0 {
 	__u32 ilength;
 	__u64 ioffset;
 	__u64 pushbuf;
+	__u64 vm;
+};
+
+struct fermi_channel_gpfifo_v0 {
+	__u8  version;
+	__u8  chid;
+	__u8  pad02[2];
+	__u32 ilength;
+	__u64 ioffset;
+	__u64 vm;
 };
 
 struct kepler_channel_gpfifo_a_v0 {
@@ -389,7 +408,7 @@ struct kepler_channel_gpfifo_a_v0 {
 	__u16 chid;
 	__u32 ilength;
 	__u64 ioffset;
-	__u64 pushbuf;
+	__u64 vm;
 };
 
 /*******************************************************************************

drivers/gpu/drm/nouveau/nouveau_chan.c

@@ -193,6 +193,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
 	const u16 *oclass = oclasses;
 	union {
 		struct nv50_channel_gpfifo_v0 nv50;
+		struct fermi_channel_gpfifo_v0 fermi;
 		struct kepler_channel_gpfifo_a_v0 kepler;
 	} args;
 	struct nouveau_channel *chan;
@@ -210,15 +211,23 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
 		if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
 			args.kepler.version = 0;
 			args.kepler.engine  = engine;
-			args.kepler.pushbuf = nvif_handle(&chan->push.ctxdma);
 			args.kepler.ilength = 0x02000;
 			args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
+			args.kepler.vm = 0;
 			size = sizeof(args.kepler);
+		} else
+		if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
+			args.fermi.version = 0;
+			args.fermi.ilength = 0x02000;
+			args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
+			args.fermi.vm = 0;
+			size = sizeof(args.fermi);
 		} else {
 			args.nv50.version = 0;
-			args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
 			args.nv50.ilength = 0x02000;
 			args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
+			args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
+			args.nv50.vm = 0;
 			size = sizeof(args.nv50);
 		}
 
@@ -227,6 +236,9 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
 		if (ret == 0) {
 			if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
 				chan->chid = args.kepler.chid;
+			else
+			if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
+				chan->chid = args.fermi.chid;
 			else
 				chan->chid = args.nv50.chid;
 			return ret;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c

@@ -76,23 +76,25 @@ nvkm_fifo_channel_create_(struct nvkm_object *parent,
 		return ret;
 
 	/* validate dma object representing push buffer */
-	handle = nvkm_client_search(client, pushbuf);
-	if (!handle)
-		return -ENOENT;
-	dmaobj = (void *)handle->object;
-
-	dmaeng = (void *)dmaobj->base.engine;
-	switch (dmaobj->base.oclass->handle) {
-	case NV_DMA_FROM_MEMORY:
-	case NV_DMA_IN_MEMORY:
-		break;
-	default:
-		return -EINVAL;
-	}
+	if (pushbuf) {
+		handle = nvkm_client_search(client, pushbuf);
+		if (!handle)
+			return -ENOENT;
+		dmaobj = (void *)handle->object;
+
+		dmaeng = (void *)dmaobj->base.engine;
+		switch (dmaobj->base.oclass->handle) {
+		case NV_DMA_FROM_MEMORY:
+		case NV_DMA_IN_MEMORY:
+			break;
+		default:
+			return -EINVAL;
+		}
 
-	ret = dmaeng->bind(dmaobj, parent, &chan->pushgpu);
-	if (ret)
-		return ret;
+		ret = dmaeng->bind(dmaobj, parent, &chan->pushgpu);
+		if (ret)
+			return ret;
+	}
 
 	/* find a free fifo channel */
 	spin_lock_irqsave(&fifo->lock, flags);

drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c

@@ -173,7 +173,7 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
 		       struct nvkm_object **pobject)
 {
 	union {
-		struct nv03_channel_dma_v0 v0;
+		struct nv50_channel_dma_v0 v0;
 	} *args = data;
 	struct nvkm_bar *bar = nvkm_bar(parent);
 	struct nv50_fifo_base *base = (void *)parent;
@@ -185,6 +185,8 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
 				   "offset %016llx\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
+		if (args->v0.vm)
+			return -ENOENT;
 	} else
 		return ret;
 
@@ -262,6 +264,8 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
 				   "ioffset %016llx ilength %08x\n",
 			   args->v0.version, args->v0.pushbuf, args->v0.ioffset,
 			   args->v0.ilength);
+		if (args->v0.vm)
+			return -ENOENT;
 	} else
 		return ret;
 

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c

@@ -199,7 +199,7 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		     struct nvkm_object **pobject)
 {
 	union {
-		struct nv50_channel_gpfifo_v0 v0;
+		struct fermi_channel_gpfifo_v0 v0;
 	} *args = data;
 	struct nvkm_bar *bar = nvkm_bar(parent);
 	struct gf100_fifo *fifo = (void *)engine;
@@ -211,16 +211,17 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %llx "
+		nvif_ioctl(parent, "create channel gpfifo vers %d "
 				   "ioffset %016llx ilength %08x\n",
-			   args->v0.version, args->v0.pushbuf, args->v0.ioffset,
+			   args->v0.version, args->v0.ioffset,
 			   args->v0.ilength);
+		if (args->v0.vm)
+			return -ENOENT;
 	} else
 		return ret;
 
 	ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
-				       fifo->user.bar.offset, 0x1000,
-				       args->v0.pushbuf,
+				       fifo->user.bar.offset, 0x1000, 0,
 				       (1ULL << NVDEV_ENGINE_SW) |
 				       (1ULL << NVDEV_ENGINE_GR) |
 				       (1ULL << NVDEV_ENGINE_CE0) |

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

@@ -252,10 +252,12 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
-		nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %llx "
+		nvif_ioctl(parent, "create channel gpfifo vers %d "
 				   "ioffset %016llx ilength %08x engine %08x\n",
-			   args->v0.version, args->v0.pushbuf, args->v0.ioffset,
+			   args->v0.version, args->v0.ioffset,
 			   args->v0.ilength, args->v0.engine);
+		if (args->v0.vm)
+			return -ENOENT;
 	} else
 		return ret;
 
@@ -282,8 +284,7 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	i = __ffs(engines);
 
 	ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
-				       fifo->user.bar.offset, 0x200,
-				       args->v0.pushbuf,
+				       fifo->user.bar.offset, 0x200, 0,
 				       fifo_engine[i].mask, &chan);
 	*pobject = nv_object(chan);
 	if (ret)

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c

@@ -121,7 +121,7 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent,
 	nvif_ioctl(parent, "create channel dma size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
-				   "offset %016llx\n", args->v0.version,
+				   "offset %08x\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
 	} else
 		return ret;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c

@@ -65,7 +65,7 @@ nv10_fifo_chan_ctor(struct nvkm_object *parent,
 	nvif_ioctl(parent, "create channel dma size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
-				   "offset %016llx\n", args->v0.version,
+				   "offset %08x\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
 	} else
 		return ret;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c

@@ -70,7 +70,7 @@ nv17_fifo_chan_ctor(struct nvkm_object *parent,
 	nvif_ioctl(parent, "create channel dma size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
-				   "offset %016llx\n", args->v0.version,
+				   "offset %08x\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
 	} else
 		return ret;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c

@@ -193,7 +193,7 @@ nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	nvif_ioctl(parent, "create channel dma size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
-				   "offset %016llx\n", args->v0.version,
+				   "offset %08x\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
 	} else
 		return ret;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c

@@ -203,7 +203,7 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
 			struct nvkm_object **pobject)
 {
 	union {
-		struct nv03_channel_dma_v0 v0;
+		struct nv50_channel_dma_v0 v0;
 	} *args = data;
 	struct nvkm_bar *bar = nvkm_bar(parent);
 	struct nv50_fifo_base *base = (void *)parent;
@@ -215,6 +215,8 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
 		nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
 				   "offset %016llx\n", args->v0.version,
 			   args->v0.pushbuf, args->v0.offset);
+		if (args->v0.vm)
+			return -ENOENT;
 	} else
 		return ret;
 
@@ -280,6 +282,8 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
 				   "ioffset %016llx ilength %08x\n",
 			   args->v0.version, args->v0.pushbuf, args->v0.ioffset,
 			   args->v0.ilength);
+		if (args->v0.vm)
+			return -ENOENT;
 	} else
 		return ret;