Commit 165f2d28 authored by Liu Yibin's avatar Liu Yibin Committed by Guo Ren

csky: Fixup msa highest 3 bits mask

Just as comment mentioned, the msa format:

 cr<30/31, 15> MSA register format:
 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
   BA     Reserved  SH  WA  B   SO SEC  C   D   V

So we should shift 29 bits not 28 bits for mask
Signed-off-by: default avatarLiu Yibin <jiulong@linux.alibaba.com>
Signed-off-by: default avatarGuo Ren <guoren@linux.alibaba.com>
parent c2e59d1f
......@@ -167,8 +167,8 @@
* BA Reserved C D V
*/
cprcr r6, cpcr30
lsri r6, 28
lsli r6, 28
lsri r6, 29
lsli r6, 29
addi r6, 0xe
cpwcr r6, cpcr30
......
......@@ -285,8 +285,8 @@
*/
mfcr r6, cr<30, 15> /* Get MSA0 */
2:
lsri r6, 28
lsli r6, 28
lsri r6, 29
lsli r6, 29
addi r6, 0x1ce
mtcr r6, cr<30, 15> /* Set MSA0 */
......
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