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Commit 19882b84 authored by Maxime Ripard's avatar Maxime Ripard
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ARM: sunxi: DT: Convert the DTs to use the GIC headers 

The GIC requires some extra opaque arguments to set the IRQ type and flags.

Convert the DTs to using the common defines.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 092a0c3b
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Showing with 158 additions and 148 deletions
arch/arm/boot/dts/sun6i-a31.dtsi
View file @ 19882b84
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arch/arm/boot/dts/sun7i-a20.dtsi
View file @ 19882b84
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arch/arm/boot/dts/sun8i-a23.dtsi
View file @ 19882b84
...@@ -49,6 +49,8 @@ ...@@ -49,6 +49,8 @@
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pinctrl/sun4i-a10.h>
/ { / {
...@@ -244,7 +246,7 @@ soc@01c00000 { ...@@ -244,7 +246,7 @@ soc@01c00000 {
dma: dma-controller@01c02000 { dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-a23-dma"; compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>; reg = <0x01c02000 0x1000>;
interrupts = <0 50 4>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 6>; clocks = <&ahb1_gates 6>;
resets = <&ahb1_rst 6>; resets = <&ahb1_rst 6>;
#dma-cells = <1>; #dma-cells = <1>;
...@@ -257,7 +259,7 @@ mmc0: mmc@01c0f000 { ...@@ -257,7 +259,7 @@ mmc0: mmc@01c0f000 {
clock-names = "ahb", "mmc"; clock-names = "ahb", "mmc";
resets = <&ahb1_rst 8>; resets = <&ahb1_rst 8>;
reset-names = "ahb"; reset-names = "ahb";
interrupts = <0 60 4>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
...@@ -268,7 +270,7 @@ mmc1: mmc@01c10000 { ...@@ -268,7 +270,7 @@ mmc1: mmc@01c10000 {
clock-names = "ahb", "mmc"; clock-names = "ahb", "mmc";
resets = <&ahb1_rst 9>; resets = <&ahb1_rst 9>;
reset-names = "ahb"; reset-names = "ahb";
interrupts = <0 61 4>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
...@@ -279,16 +281,16 @@ mmc2: mmc@01c11000 { ...@@ -279,16 +281,16 @@ mmc2: mmc@01c11000 {
clock-names = "ahb", "mmc"; clock-names = "ahb", "mmc";
resets = <&ahb1_rst 10>; resets = <&ahb1_rst 10>;
reset-names = "ahb"; reset-names = "ahb";
interrupts = <0 62 4>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
pio: pinctrl@01c20800 { pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a23-pinctrl"; compatible = "allwinner,sun8i-a23-pinctrl";
reg = <0x01c20800 0x400>; reg = <0x01c20800 0x400>;
interrupts = <0 11 4>, interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0 15 4>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0 17 4>; <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 5>; clocks = <&apb1_gates 5>;
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
...@@ -360,21 +362,21 @@ apb2_rst: reset@01c202d8 { ...@@ -360,21 +362,21 @@ apb2_rst: reset@01c202d8 {
timer@01c20c00 { timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer"; compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>; reg = <0x01c20c00 0xa0>;
interrupts = <0 18 4>, interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<0 19 4>; <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>; clocks = <&osc24M>;
}; };
wdt0: watchdog@01c20ca0 { wdt0: watchdog@01c20ca0 {
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>; reg = <0x01c20ca0 0x20>;
interrupts = <0 25 4>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
}; };
uart0: serial@01c28000 { uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>; reg = <0x01c28000 0x400>;
interrupts = <0 0 4>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 16>; clocks = <&apb2_gates 16>;
...@@ -387,7 +389,7 @@ uart0: serial@01c28000 { ...@@ -387,7 +389,7 @@ uart0: serial@01c28000 {
uart1: serial@01c28400 { uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>; reg = <0x01c28400 0x400>;
interrupts = <0 1 4>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 17>; clocks = <&apb2_gates 17>;
...@@ -400,7 +402,7 @@ uart1: serial@01c28400 { ...@@ -400,7 +402,7 @@ uart1: serial@01c28400 {
uart2: serial@01c28800 { uart2: serial@01c28800 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>; reg = <0x01c28800 0x400>;
interrupts = <0 2 4>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 18>; clocks = <&apb2_gates 18>;
...@@ -413,7 +415,7 @@ uart2: serial@01c28800 { ...@@ -413,7 +415,7 @@ uart2: serial@01c28800 {
uart3: serial@01c28c00 { uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>; reg = <0x01c28c00 0x400>;
interrupts = <0 3 4>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 19>; clocks = <&apb2_gates 19>;
...@@ -426,7 +428,7 @@ uart3: serial@01c28c00 { ...@@ -426,7 +428,7 @@ uart3: serial@01c28c00 {
uart4: serial@01c29000 { uart4: serial@01c29000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>; reg = <0x01c29000 0x400>;
interrupts = <0 4 4>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb2_gates 20>; clocks = <&apb2_gates 20>;
...@@ -439,7 +441,7 @@ uart4: serial@01c29000 { ...@@ -439,7 +441,7 @@ uart4: serial@01c29000 {
i2c0: i2c@01c2ac00 { i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>; reg = <0x01c2ac00 0x400>;
interrupts = <0 6 4>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 0>; clocks = <&apb2_gates 0>;
resets = <&apb2_rst 0>; resets = <&apb2_rst 0>;
status = "disabled"; status = "disabled";
...@@ -450,7 +452,7 @@ i2c0: i2c@01c2ac00 { ...@@ -450,7 +452,7 @@ i2c0: i2c@01c2ac00 {
i2c1: i2c@01c2b000 { i2c1: i2c@01c2b000 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>; reg = <0x01c2b000 0x400>;
interrupts = <0 7 4>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 1>; clocks = <&apb2_gates 1>;
resets = <&apb2_rst 1>; resets = <&apb2_rst 1>;
status = "disabled"; status = "disabled";
...@@ -461,7 +463,7 @@ i2c1: i2c@01c2b000 { ...@@ -461,7 +463,7 @@ i2c1: i2c@01c2b000 {
i2c2: i2c@01c2b400 { i2c2: i2c@01c2b400 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>; reg = <0x01c2b400 0x400>;
interrupts = <0 8 4>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 2>; clocks = <&apb2_gates 2>;
resets = <&apb2_rst 2>; resets = <&apb2_rst 2>;
status = "disabled"; status = "disabled";
...@@ -477,13 +479,14 @@ gic: interrupt-controller@01c81000 { ...@@ -477,13 +479,14 @@ gic: interrupt-controller@01c81000 {
<0x01c86000 0x2000>; <0x01c86000 0x2000>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <1 9 0xf04>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
rtc: rtc@01f00000 { rtc: rtc@01f00000 {
compatible = "allwinner,sun6i-a31-rtc"; compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>; reg = <0x01f00000 0x54>;
interrupts = <0 40 4>, <0 41 4>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
}; };
prcm@01f01400 { prcm@01f01400 {
...@@ -533,7 +536,7 @@ apb0_rst: apb0_rst { ...@@ -533,7 +536,7 @@ apb0_rst: apb0_rst {
r_uart: serial@01f02800 { r_uart: serial@01f02800 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x01f02800 0x400>; reg = <0x01f02800 0x400>;
interrupts = <0 38 4>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb0_gates 4>; clocks = <&apb0_gates 4>;
...@@ -544,7 +547,7 @@ r_uart: serial@01f02800 { ...@@ -544,7 +547,7 @@ r_uart: serial@01f02800 {
r_pio: pinctrl@01f02c00 { r_pio: pinctrl@01f02c00 {
compatible = "allwinner,sun8i-a23-r-pinctrl"; compatible = "allwinner,sun8i-a23-r-pinctrl";
reg = <0x01f02c00 0x400>; reg = <0x01f02c00 0x400>;
interrupts = <0 45 4>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>; clocks = <&apb0_gates 0>;
resets = <&apb0_rst 0>; resets = <&apb0_rst 0>;
gpio-controller; gpio-controller;
......
arch/arm/boot/dts/sun9i-a80.dtsi
View file @ 19882b84
...@@ -49,6 +49,8 @@ ...@@ -49,6 +49,8 @@
#include "skeleton64.dtsi" #include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pinctrl/sun4i-a10.h>
/ { / {
...@@ -293,7 +295,7 @@ gic: interrupt-controller@01c41000 { ...@@ -293,7 +295,7 @@ gic: interrupt-controller@01c41000 {
<0x01c46000 0x2000>; <0x01c46000 0x2000>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupts = <1 9 0xf04>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
ahb0_resets: reset@060005a0 { ahb0_resets: reset@060005a0 {
...@@ -329,12 +331,12 @@ apb1_resets: reset@060005b4 { ...@@ -329,12 +331,12 @@ apb1_resets: reset@060005b4 {
timer@06000c00 { timer@06000c00 {
compatible = "allwinner,sun4i-a10-timer"; compatible = "allwinner,sun4i-a10-timer";
reg = <0x06000c00 0xa0>; reg = <0x06000c00 0xa0>;
interrupts = <0 18 4>, interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<0 19 4>, <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<0 20 4>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<0 21 4>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<0 22 4>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<0 23 4>; <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>; clocks = <&osc24M>;
}; };
...@@ -342,11 +344,11 @@ timer@06000c00 { ...@@ -342,11 +344,11 @@ timer@06000c00 {
pio: pinctrl@06000800 { pio: pinctrl@06000800 {
compatible = "allwinner,sun9i-a80-pinctrl"; compatible = "allwinner,sun9i-a80-pinctrl";
reg = <0x06000800 0x400>; reg = <0x06000800 0x400>;
interrupts = <0 11 4>, interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0 15 4>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0 16 4>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 4>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<0 120 4>; <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 5>; clocks = <&apb0_gates 5>;
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
...@@ -379,7 +381,7 @@ uart4_pins_a: uart4@0 { ...@@ -379,7 +381,7 @@ uart4_pins_a: uart4@0 {
uart0: serial@07000000 { uart0: serial@07000000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x07000000 0x400>; reg = <0x07000000 0x400>;
interrupts = <0 0 4>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 16>; clocks = <&apb1_gates 16>;
...@@ -390,7 +392,7 @@ uart0: serial@07000000 { ...@@ -390,7 +392,7 @@ uart0: serial@07000000 {
uart1: serial@07000400 { uart1: serial@07000400 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x07000400 0x400>; reg = <0x07000400 0x400>;
interrupts = <0 1 4>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 17>; clocks = <&apb1_gates 17>;
...@@ -401,7 +403,7 @@ uart1: serial@07000400 { ...@@ -401,7 +403,7 @@ uart1: serial@07000400 {
uart2: serial@07000800 { uart2: serial@07000800 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x07000800 0x400>; reg = <0x07000800 0x400>;
interrupts = <0 2 4>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 18>; clocks = <&apb1_gates 18>;
...@@ -412,7 +414,7 @@ uart2: serial@07000800 { ...@@ -412,7 +414,7 @@ uart2: serial@07000800 {
uart3: serial@07000c00 { uart3: serial@07000c00 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x07000c00 0x400>; reg = <0x07000c00 0x400>;
interrupts = <0 3 4>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 19>; clocks = <&apb1_gates 19>;
...@@ -423,7 +425,7 @@ uart3: serial@07000c00 { ...@@ -423,7 +425,7 @@ uart3: serial@07000c00 {
uart4: serial@07001000 { uart4: serial@07001000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x07001000 0x400>; reg = <0x07001000 0x400>;
interrupts = <0 4 4>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 20>; clocks = <&apb1_gates 20>;
...@@ -434,7 +436,7 @@ uart4: serial@07001000 { ...@@ -434,7 +436,7 @@ uart4: serial@07001000 {
uart5: serial@07001400 { uart5: serial@07001400 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x07001400 0x400>; reg = <0x07001400 0x400>;
interrupts = <0 5 4>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 21>; clocks = <&apb1_gates 21>;
...@@ -445,7 +447,7 @@ uart5: serial@07001400 { ...@@ -445,7 +447,7 @@ uart5: serial@07001400 {
i2c0: i2c@07002800 { i2c0: i2c@07002800 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002800 0x400>; reg = <0x07002800 0x400>;
interrupts = <0 6 4>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 0>; clocks = <&apb1_gates 0>;
resets = <&apb1_resets 0>; resets = <&apb1_resets 0>;
status = "disabled"; status = "disabled";
...@@ -456,7 +458,7 @@ i2c0: i2c@07002800 { ...@@ -456,7 +458,7 @@ i2c0: i2c@07002800 {
i2c1: i2c@07002c00 { i2c1: i2c@07002c00 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002c00 0x400>; reg = <0x07002c00 0x400>;
interrupts = <0 7 4>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 1>; clocks = <&apb1_gates 1>;
resets = <&apb1_resets 1>; resets = <&apb1_resets 1>;
status = "disabled"; status = "disabled";
...@@ -467,7 +469,7 @@ i2c1: i2c@07002c00 { ...@@ -467,7 +469,7 @@ i2c1: i2c@07002c00 {
i2c2: i2c@07003000 { i2c2: i2c@07003000 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003000 0x400>; reg = <0x07003000 0x400>;
interrupts = <0 8 4>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 2>; clocks = <&apb1_gates 2>;
resets = <&apb1_resets 2>; resets = <&apb1_resets 2>;
status = "disabled"; status = "disabled";
...@@ -478,7 +480,7 @@ i2c2: i2c@07003000 { ...@@ -478,7 +480,7 @@ i2c2: i2c@07003000 {
i2c3: i2c@07003400 { i2c3: i2c@07003400 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003400 0x400>; reg = <0x07003400 0x400>;
interrupts = <0 9 4>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 3>; clocks = <&apb1_gates 3>;
resets = <&apb1_resets 3>; resets = <&apb1_resets 3>;
status = "disabled"; status = "disabled";
...@@ -489,7 +491,7 @@ i2c3: i2c@07003400 { ...@@ -489,7 +491,7 @@ i2c3: i2c@07003400 {
i2c4: i2c@07003800 { i2c4: i2c@07003800 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003800 0x400>; reg = <0x07003800 0x400>;
interrupts = <0 10 4>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 4>; clocks = <&apb1_gates 4>;
resets = <&apb1_resets 4>; resets = <&apb1_resets 4>;
status = "disabled"; status = "disabled";
...@@ -500,13 +502,13 @@ i2c4: i2c@07003800 { ...@@ -500,13 +502,13 @@ i2c4: i2c@07003800 {
r_wdt: watchdog@08001000 { r_wdt: watchdog@08001000 {
compatible = "allwinner,sun6i-a31-wdt"; compatible = "allwinner,sun6i-a31-wdt";
reg = <0x08001000 0x20>; reg = <0x08001000 0x20>;
interrupts = <0 36 4>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
}; };
r_uart: serial@08002800 { r_uart: serial@08002800 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x08002800 0x400>; reg = <0x08002800 0x400>;
interrupts = <0 38 4>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&osc24M>; clocks = <&osc24M>;
......
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