Skip to content

L
linux
Commit 1ab4a546 authored by Jean Tourrilhes's avatar Jean Tourrilhes Committed by David S. Miller
Browse files
Options

[IRDA]: Move IRDA device headers to more appropriate place.

parent 6f5abb00
Hide whitespace changes
Inline Side-by-side
Showing with 8 additions and 354 deletions
drivers/net/irda/ali-ircc.c
View file @ 1ab4a546
......@@ -44,7 +44,7 @@
#include <net/irda/irda.h>
#include <net/irda/irda_device.h>
#include <net/irda/ali-ircc.h>
#include "ali-ircc.h"
#define CHIP_IO_EXTENT 8
#define BROKEN_DONGLE_ID
......
drivers/net/irda/au1k_ir.c
View file @ 1ab4a546
......@@ -52,7 +52,7 @@
#include <net/irda/irmod.h>
#include <net/irda/wrapper.h>
#include <net/irda/irda_device.h>
#include "net/irda/au1000_ircc.h"
#include "au1000_ircc.h"
static int au1k_irda_net_init(struct net_device *);
static int au1k_irda_start(struct net_device *);
......
drivers/net/irda/irda-usb.c
View file @ 1ab4a546
......@@ -62,7 +62,7 @@
#include <linux/rtnetlink.h>
#include <linux/usb.h>
#include <net/irda/irda-usb.h>
#include "irda-usb.h"
/*------------------------------------------------------------------*/
......
drivers/net/irda/irport.c
View file @ 1ab4a546
......@@ -58,7 +58,7 @@
#include <net/irda/irda.h>
#include <net/irda/wrapper.h>
#include <net/irda/irport.h>
#include "irport.h"
#define IO_EXTENT 8
......
drivers/net/irda/nsc-ircc.c
View file @ 1ab4a546
......@@ -63,7 +63,7 @@
#include <net/irda/irda.h>
#include <net/irda/irda_device.h>
#include <net/irda/nsc-ircc.h>
#include "nsc-ircc.h"
#define CHIP_IO_EXTENT 8
#define BROKEN_DONGLE_ID
......
drivers/net/irda/vlsi_ir.c
View file @ 1ab4a546
......@@ -53,7 +53,7 @@ MODULE_LICENSE("GPL");
#include <net/irda/wrapper.h>
#include <net/irda/crc.h>
#include <net/irda/vlsi_ir.h>
#include "vlsi_ir.h"
/********************************************************/
......
drivers/net/irda/w83977af_ir.c
View file @ 1ab4a546
......@@ -58,8 +58,8 @@
#include <net/irda/irda.h>
#include <net/irda/wrapper.h>
#include <net/irda/irda_device.h>
#include <net/irda/w83977af.h>
#include <net/irda/w83977af_ir.h>
#include "w83977af.h"
#include "w83977af_ir.h"
#ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
#undef CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */
......
include/net/irda/smc-ircc.h deleted 100644 → 0
View file @ 6f5abb00
/*********************************************************************
*
* Filename: smc-ircc.h
* Version: 0.3
* Description: Definitions for the SMC IrCC chipset
* Status: Experimental.
* Author: Thomas Davis (tadavis@jps.net)
*
* Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no>
* Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net>
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************/
#ifndef SMC_IRCC_H
#define SMC_IRCC_H
#include <linux/spinlock.h>
#include <linux/pm.h>
#include <net/irda/irport.h>
/* DMA modes needed */
#define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
#define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
/* Master Control Register */
#define IRCC_MASTER 0x07
#define IRCC_MASTER_POWERDOWN 0x80
#define IRCC_MASTER_RESET 0x40
#define IRCC_MASTER_INT_EN 0x20
#define IRCC_MASTER_ERROR_RESET 0x10
/* Register block 0 */
/* Interrupt Identification */
#define IRCC_IIR 0x01
#define IRCC_IIR_ACTIVE_FRAME 0x80
#define IRCC_IIR_EOM 0x40
#define IRCC_IIR_RAW_MODE 0x20
#define IRCC_IIR_FIFO 0x10
/* Interrupt Enable */
#define IRCC_IER 0x02
#define IRCC_IER_ACTIVE_FRAME 0x80
#define IRCC_IER_EOM 0x40
#define IRCC_IER_RAW_MODE 0x20
#define IRCC_IER_FIFO 0x10
/* Line Status Register */
#define IRCC_LSR 0x03
#define IRCC_LSR_UNDERRUN 0x80
#define IRCC_LSR_OVERRUN 0x40
#define IRCC_LSR_FRAME_ERROR 0x20
#define IRCC_LSR_SIZE_ERROR 0x10
#define IRCC_LSR_CRC_ERROR 0x80
#define IRCC_LSR_FRAME_ABORT 0x40
/* Line Control Register A */
#define IRCC_LCR_A 0x04
#define IRCC_LCR_A_FIFO_RESET 0x80
#define IRCC_LCR_A_FAST 0x40
#define IRCC_LCR_A_GP_DATA 0x20
#define IRCC_LCR_A_RAW_TX 0x10
#define IRCC_LCR_A_RAW_RX 0x08
#define IRCC_LCR_A_ABORT 0x04
#define IRCC_LCR_A_DATA_DONE 0x02
/* Line Control Register B */
#define IRCC_LCR_B 0x05
#define IRCC_LCR_B_SCE_DISABLED 0x00
#define IRCC_LCR_B_SCE_TRANSMIT 0x40
#define IRCC_LCR_B_SCE_RECEIVE 0x80
#define IRCC_LCR_B_SCE_UNDEFINED 0xc0
#define IRCC_LCR_B_SIP_ENABLE 0x20
#define IRCC_LCR_B_BRICK_WALL 0x10
/* Bus Status Register */
#define IRCC_BSR 0x06
#define IRCC_BSR_NOT_EMPTY 0x80
#define IRCC_BSR_FIFO_FULL 0x40
#define IRCC_BSR_TIMEOUT 0x20
/* Register block 1 */
#define IRCC_FIFO_THRESHOLD 0x02
#define IRCC_SCE_CFGA 0x00
#define IRCC_CFGA_AUX_IR 0x80
#define IRCC_CFGA_HALF_DUPLEX 0x04
#define IRCC_CFGA_TX_POLARITY 0x02
#define IRCC_CFGA_RX_POLARITY 0x01
#define IRCC_CFGA_COM 0x00
#define IRCC_CFGA_IRDA_SIR_A 0x08
#define IRCC_CFGA_ASK_SIR 0x10
#define IRCC_CFGA_IRDA_SIR_B 0x18
#define IRCC_CFGA_IRDA_HDLC 0x20
#define IRCC_CFGA_IRDA_4PPM 0x28
#define IRCC_CFGA_CONSUMER 0x30
#define IRCC_CFGA_RAW_IR 0x38
#define IRCC_CFGA_OTHER 0x40
#define IRCC_IR_HDLC 0x04
#define IRCC_IR_4PPM 0x01
#define IRCC_IR_CONSUMER 0x02
#define IRCC_SCE_CFGB 0x01
#define IRCC_CFGB_LOOPBACK 0x20
#define IRCC_CFGB_LPBCK_TX_CRC 0x10
#define IRCC_CFGB_NOWAIT 0x08
#define IRCC_CFGB_STRING_MOVE 0x04
#define IRCC_CFGB_DMA_BURST 0x02
#define IRCC_CFGB_DMA_ENABLE 0x01
#define IRCC_CFGB_MUX_COM 0x00
#define IRCC_CFGB_MUX_IR 0x40
#define IRCC_CFGB_MUX_AUX 0x80
#define IRCC_CFGB_MUX_INACTIVE 0xc0
/* Register block 3 - Identification Registers! */
#define IRCC_ID_HIGH 0x00 /* 0x10 */
#define IRCC_ID_LOW 0x01 /* 0xB8 */
#define IRCC_CHIP_ID 0x02 /* 0xF1 */
#define IRCC_VERSION 0x03 /* 0x01 */
#define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */
/* Register block 4 - IrDA */
#define IRCC_CONTROL 0x00
#define IRCC_BOF_COUNT_LO 0x01 /* Low byte */
#define IRCC_BOF_COUNT_HI 0x00 /* High nibble (bit 0-3) */
#define IRCC_BRICKWALL_CNT_LO 0x02 /* Low byte */
#define IRCC_BRICKWALL_CNT_HI 0x03 /* High nibble (bit 4-7) */
#define IRCC_TX_SIZE_LO 0x04 /* Low byte */
#define IRCC_TX_SIZE_HI 0x03 /* High nibble (bit 0-3) */
#define IRCC_RX_SIZE_HI 0x05 /* High nibble (bit 0-3) */
#define IRCC_RX_SIZE_LO 0x06 /* Low byte */
#define IRCC_1152 0x80
#define IRCC_CRC 0x40
/* Private data for each instance */
struct ircc_cb {
struct net_device *netdev; /* Yes! we are some kind of netdevice */
struct irlap_cb *irlap; /* The link layer we are binded to */
chipio_t *io; /* IrDA controller information */
iobuff_t tx_buff; /* Transmit buffer */
iobuff_t rx_buff; /* Receive buffer */
struct irport_cb *irport;
/* Locking : half of our operations are done with irport, so we
* use the irport spinlock to make sure *everything* is properly
* synchronised - Jean II */
__u32 new_speed;
int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
int tx_len; /* Number of frames in tx_buff */
struct pm_dev *pmdev;
};
#endif /* SMC_IRCC_H */
include/net/irda/toshoboe.h deleted 100644 → 0
View file @ 6f5abb00
/*********************************************************************
*
* Filename: toshoboe.h
* Version: 0.1
* Description: Driver for the Toshiba OBOE (or type-O)
* FIR Chipset.
* Status: Experimental.
* Author: James McKenzie <james@fishsoup.dhs.org>
* Created at: Sat May 8 12:35:27 1999
*
* Copyright (c) 1999-2000 James McKenzie, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Neither James McKenzie nor Cambridge University admit liability nor
* provide warranty for any of this software. This material is
* provided "AS-IS" and at no charge.
*
* Applicable Models : Libretto 100CT. and many more
*
********************************************************************/
#ifndef TOSHOBOE_H
#define TOSHOBOE_H
/* Registers */
/*Receive and transmit task registers (read only) */
#define OBOE_RCVT (0x00+(self->base))
#define OBOE_XMTT (0x01+(self->base))
#define OBOE_XMTT_OFFSET 0x40
/*Page pointers to the TaskFile structure */
#define OBOE_TFP2 (0x02+(self->base))
#define OBOE_TFP0 (0x04+(self->base))
#define OBOE_TFP1 (0x05+(self->base))
/*Dunno */
#define OBOE_REG_3 (0x03+(self->base))
/*Number of tasks to use in Xmit and Recv queues */
#define OBOE_NTR (0x07+(self->base))
#define OBOE_NTR_XMIT4 0x00
#define OBOE_NTR_XMIT8 0x10
#define OBOE_NTR_XMIT16 0x30
#define OBOE_NTR_XMIT32 0x70
#define OBOE_NTR_XMIT64 0xf0
#define OBOE_NTR_RECV4 0x00
#define OBOE_NTR_RECV8 0x01
#define OBOE_NTR_RECV6 0x03
#define OBOE_NTR_RECV32 0x07
#define OBOE_NTR_RECV64 0x0f
/* Dunno */
#define OBOE_REG_9 (0x09+(self->base))
/* Interrupt Status Register */
#define OBOE_ISR (0x0c+(self->base))
#define OBOE_ISR_TXDONE 0x80
#define OBOE_ISR_RXDONE 0x40
#define OBOE_ISR_20 0x20
#define OBOE_ISR_10 0x10
#define OBOE_ISR_8 0x08 /*This is collision or parity or something */
#define OBOE_ISR_4 0x08
#define OBOE_ISR_2 0x08
#define OBOE_ISR_1 0x08
/*Dunno */
#define OBOE_REG_D (0x0d+(self->base))
/*Register Lock Register */
#define OBOE_LOCK ((self->base)+0x0e)
/*Speed control registers */
#define OBOE_PMDL (0x10+(self->base))
#define OBOE_PMDL_SIR 0x18
#define OBOE_PMDL_MIR 0xa0
#define OBOE_PMDL_FIR 0x40
#define OBOE_SMDL (0x18+(self->base))
#define OBOE_SMDL_SIR 0x20
#define OBOE_SMDL_MIR 0x01
#define OBOE_SMDL_FIR 0x0f
#define OBOE_UDIV (0x19+(self->base))
/*Dunno */
#define OBOE_REG_11 (0x11+(self->base))
/*Chip Reset Register */
#define OBOE_RST (0x15+(self->base))
#define OBOE_RST_WRAP 0x8
/*Dunno */
#define OBOE_REG_1A (0x1a+(self->base))
#define OBOE_REG_1B (0x1b+(self->base))
/* The PCI ID of the OBOE chip */
#ifndef PCI_DEVICE_ID_FIR701
#define PCI_DEVICE_ID_FIR701 0x0701
#endif
typedef unsigned int dword;
typedef unsigned short int word;
typedef unsigned char byte;
typedef dword Paddr;
struct OboeTask
{
__u16 len;
__u8 unused;
__u8 control;
__u32 buffer;
};
#define OBOE_NTASKS 64
struct OboeTaskFile
{
struct OboeTask recv[OBOE_NTASKS];
struct OboeTask xmit[OBOE_NTASKS];
};
#define OBOE_TASK_BUF_LEN (sizeof(struct OboeTaskFile) << 1)
/*These set the number of slots in use */
#define TX_SLOTS 4
#define RX_SLOTS 4
/* You need also to change this, toshiba uses 4,8 and 4,4 */
/* It makes no difference if you are only going to use ONETASK mode */
/* remember each buffer use XX_BUF_SZ more _PHYSICAL_ memory */
#define OBOE_NTR_VAL (OBOE_NTR_XMIT4 | OBOE_NTR_RECV4)
struct toshoboe_cb
{
struct net_device *netdev; /* Yes! we are some kind of netdevice */
struct net_device_stats stats;
struct irlap_cb *irlap; /* The link layer we are binded to */
struct qos_info qos; /* QoS capabilities for this device */
chipio_t io; /* IrDA controller information */
__u32 new_speed;
struct pci_dev *pdev; /*PCI device */
int base; /*IO base */
int txpending; /*how many tx's are pending */
int txs, rxs; /*Which slots are we at */
void *taskfilebuf; /*The unaligned taskfile buffer */
struct OboeTaskFile *taskfile; /*The taskfile */
void *xmit_bufs[TX_SLOTS]; /*The buffers */
void *recv_bufs[RX_SLOTS];
int open;
int stopped; /*Stopped by some or other APM stuff*/
};
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7