Commit 1ac4329a authored by Denis Bolotin's avatar Denis Bolotin Committed by David S. Miller

qed: Add configuration information to register dump and debug data

Configuration information is added to the debug data collection, in
addition to register dump.
Added qed_dbg_nvm_image() that receives an image type, allocates a
buffer and reads the image. The images are saved in the buffers and the
dump size is updated.
Signed-off-by: default avatarDenis Bolotin <denis.bolotin@cavium.com>
Signed-off-by: default avatarAriel Elior <ariel.elior@cavium.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b60bfdfe
...@@ -7778,6 +7778,57 @@ int qed_dbg_igu_fifo_size(struct qed_dev *cdev) ...@@ -7778,6 +7778,57 @@ int qed_dbg_igu_fifo_size(struct qed_dev *cdev)
return qed_dbg_feature_size(cdev, DBG_FEATURE_IGU_FIFO); return qed_dbg_feature_size(cdev, DBG_FEATURE_IGU_FIFO);
} }
int qed_dbg_nvm_image_length(struct qed_hwfn *p_hwfn,
enum qed_nvm_images image_id, u32 *length)
{
struct qed_nvm_image_att image_att;
int rc;
*length = 0;
rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
if (rc)
return rc;
*length = image_att.length;
return rc;
}
int qed_dbg_nvm_image(struct qed_dev *cdev, void *buffer,
u32 *num_dumped_bytes, enum qed_nvm_images image_id)
{
struct qed_hwfn *p_hwfn =
&cdev->hwfns[cdev->dbg_params.engine_for_debug];
u32 len_rounded, i;
__be32 val;
int rc;
*num_dumped_bytes = 0;
rc = qed_dbg_nvm_image_length(p_hwfn, image_id, &len_rounded);
if (rc)
return rc;
DP_NOTICE(p_hwfn->cdev,
"Collecting a debug feature [\"nvram image %d\"]\n",
image_id);
len_rounded = roundup(len_rounded, sizeof(u32));
rc = qed_mcp_get_nvm_image(p_hwfn, image_id, buffer, len_rounded);
if (rc)
return rc;
/* QED_NVM_IMAGE_NVM_META image is not swapped like other images */
if (image_id != QED_NVM_IMAGE_NVM_META)
for (i = 0; i < len_rounded; i += 4) {
val = cpu_to_be32(*(u32 *)(buffer + i));
*(u32 *)(buffer + i) = val;
}
*num_dumped_bytes = len_rounded;
return rc;
}
int qed_dbg_protection_override(struct qed_dev *cdev, void *buffer, int qed_dbg_protection_override(struct qed_dev *cdev, void *buffer,
u32 *num_dumped_bytes) u32 *num_dumped_bytes)
{ {
...@@ -7831,6 +7882,9 @@ enum debug_print_features { ...@@ -7831,6 +7882,9 @@ enum debug_print_features {
IGU_FIFO = 6, IGU_FIFO = 6,
PHY = 7, PHY = 7,
FW_ASSERTS = 8, FW_ASSERTS = 8,
NVM_CFG1 = 9,
DEFAULT_CFG = 10,
NVM_META = 11,
}; };
static u32 qed_calc_regdump_header(enum debug_print_features feature, static u32 qed_calc_regdump_header(enum debug_print_features feature,
...@@ -7965,13 +8019,61 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) ...@@ -7965,13 +8019,61 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc); DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc);
} }
/* nvm cfg1 */
rc = qed_dbg_nvm_image(cdev,
(u8 *)buffer + offset + REGDUMP_HEADER_SIZE,
&feature_size, QED_NVM_IMAGE_NVM_CFG1);
if (!rc) {
*(u32 *)((u8 *)buffer + offset) =
qed_calc_regdump_header(NVM_CFG1, cur_engine,
feature_size, omit_engine);
offset += (feature_size + REGDUMP_HEADER_SIZE);
} else if (rc != -ENOENT) {
DP_ERR(cdev,
"qed_dbg_nvm_image failed for image %d (%s), rc = %d\n",
QED_NVM_IMAGE_NVM_CFG1, "QED_NVM_IMAGE_NVM_CFG1", rc);
}
/* nvm default */
rc = qed_dbg_nvm_image(cdev,
(u8 *)buffer + offset + REGDUMP_HEADER_SIZE,
&feature_size, QED_NVM_IMAGE_DEFAULT_CFG);
if (!rc) {
*(u32 *)((u8 *)buffer + offset) =
qed_calc_regdump_header(DEFAULT_CFG, cur_engine,
feature_size, omit_engine);
offset += (feature_size + REGDUMP_HEADER_SIZE);
} else if (rc != -ENOENT) {
DP_ERR(cdev,
"qed_dbg_nvm_image failed for image %d (%s), rc = %d\n",
QED_NVM_IMAGE_DEFAULT_CFG, "QED_NVM_IMAGE_DEFAULT_CFG",
rc);
}
/* nvm meta */
rc = qed_dbg_nvm_image(cdev,
(u8 *)buffer + offset + REGDUMP_HEADER_SIZE,
&feature_size, QED_NVM_IMAGE_NVM_META);
if (!rc) {
*(u32 *)((u8 *)buffer + offset) =
qed_calc_regdump_header(NVM_META, cur_engine,
feature_size, omit_engine);
offset += (feature_size + REGDUMP_HEADER_SIZE);
} else if (rc != -ENOENT) {
DP_ERR(cdev,
"qed_dbg_nvm_image failed for image %d (%s), rc = %d\n",
QED_NVM_IMAGE_NVM_META, "QED_NVM_IMAGE_NVM_META", rc);
}
return 0; return 0;
} }
int qed_dbg_all_data_size(struct qed_dev *cdev) int qed_dbg_all_data_size(struct qed_dev *cdev)
{ {
struct qed_hwfn *p_hwfn =
&cdev->hwfns[cdev->dbg_params.engine_for_debug];
u32 regs_len = 0, image_len = 0;
u8 cur_engine, org_engine; u8 cur_engine, org_engine;
u32 regs_len = 0;
org_engine = qed_get_debug_engine(cdev); org_engine = qed_get_debug_engine(cdev);
for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) {
...@@ -7993,6 +8095,15 @@ int qed_dbg_all_data_size(struct qed_dev *cdev) ...@@ -7993,6 +8095,15 @@ int qed_dbg_all_data_size(struct qed_dev *cdev)
/* Engine common */ /* Engine common */
regs_len += REGDUMP_HEADER_SIZE + qed_dbg_mcp_trace_size(cdev); regs_len += REGDUMP_HEADER_SIZE + qed_dbg_mcp_trace_size(cdev);
qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_CFG1, &image_len);
if (image_len)
regs_len += REGDUMP_HEADER_SIZE + image_len;
qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_DEFAULT_CFG, &image_len);
if (image_len)
regs_len += REGDUMP_HEADER_SIZE + image_len;
qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_META, &image_len);
if (image_len)
regs_len += REGDUMP_HEADER_SIZE + image_len;
return regs_len; return regs_len;
} }
......
...@@ -2529,7 +2529,7 @@ int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn) ...@@ -2529,7 +2529,7 @@ int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
return rc; return rc;
} }
static int int
qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
enum qed_nvm_images image_id, enum qed_nvm_images image_id,
struct qed_nvm_image_att *p_image_att) struct qed_nvm_image_att *p_image_att)
...@@ -2545,6 +2545,15 @@ qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, ...@@ -2545,6 +2545,15 @@ qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
case QED_NVM_IMAGE_FCOE_CFG: case QED_NVM_IMAGE_FCOE_CFG:
type = NVM_TYPE_FCOE_CFG; type = NVM_TYPE_FCOE_CFG;
break; break;
case QED_NVM_IMAGE_NVM_CFG1:
type = NVM_TYPE_NVM_CFG1;
break;
case QED_NVM_IMAGE_DEFAULT_CFG:
type = NVM_TYPE_DEFAULT_CFG;
break;
case QED_NVM_IMAGE_NVM_META:
type = NVM_TYPE_META;
break;
default: default:
DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
image_id); image_id);
...@@ -2588,9 +2597,6 @@ int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, ...@@ -2588,9 +2597,6 @@ int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
return -EINVAL; return -EINVAL;
} }
/* Each NVM image is suffixed by CRC; Upper-layer has no need for it */
image_att.length -= 4;
if (image_att.length > buffer_len) { if (image_att.length > buffer_len) {
DP_VERBOSE(p_hwfn, DP_VERBOSE(p_hwfn,
QED_MSG_STORAGE, QED_MSG_STORAGE,
......
...@@ -482,6 +482,20 @@ struct qed_nvm_image_att { ...@@ -482,6 +482,20 @@ struct qed_nvm_image_att {
u32 length; u32 length;
}; };
/**
* @brief Allows reading a whole nvram image
*
* @param p_hwfn
* @param image_id - image to get attributes for
* @param p_image_att - image attributes structure into which to fill data
*
* @return int - 0 - operation was successful.
*/
int
qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
enum qed_nvm_images image_id,
struct qed_nvm_image_att *p_image_att);
/** /**
* @brief Allows reading a whole nvram image * @brief Allows reading a whole nvram image
* *
......
...@@ -159,6 +159,9 @@ struct qed_dcbx_get { ...@@ -159,6 +159,9 @@ struct qed_dcbx_get {
enum qed_nvm_images { enum qed_nvm_images {
QED_NVM_IMAGE_ISCSI_CFG, QED_NVM_IMAGE_ISCSI_CFG,
QED_NVM_IMAGE_FCOE_CFG, QED_NVM_IMAGE_FCOE_CFG,
QED_NVM_IMAGE_NVM_CFG1,
QED_NVM_IMAGE_DEFAULT_CFG,
QED_NVM_IMAGE_NVM_META,
}; };
struct qed_link_eee_params { struct qed_link_eee_params {
......
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