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Commit 1cf257ab authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-dt-pm-domain-for-v4.7' of... 

Merge tag 'renesas-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late

Merge "Renesas ARM Based SoC DT PM Domain Updates for v4.7" into next/late

* Add SYSC PM Domains to DT for R-Car Gen 1 and 2 SoCs

This pull requests is based on a merge of:

* "[GIT PULL] Second Round of Renesas ARM Based SoC R-Car SYSC Updates for
  v4.7", tagged as renesas-rcar-sysc2-for-v4.7, which you have already
  pulled.
* "[GIT PULL v2] Renesas ARM Based SoC DT Updates for v4.7",
  tagged as renesas-dt-for-v4.7, which you have also already pulled.

The reason for the somewhat tedious base on
renesas-rcar-sysc2-for-v4.7, which provides driver changes,
is a hard run-time dependency.

I also have a similar set of changes for arm64 which I will send separately.

* tag 'renesas-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (88 commits)
  ARM: dts: r8a7794: Use SYSC "always-on" PM Domain
  ARM: dts: r8a7793: Use SYSC "always-on" PM Domain
  ARM: dts: r8a7791: Use SYSC "always-on" PM Domain
  ARM: dts: r8a7790: Use SYSC "always-on" PM Domain
  ARM: dts: r8a7779: Use SYSC "always-on" PM Domain
  ARM: dts: r8a7794: Add SYSC PM Domains
  ARM: dts: r8a7793: Add SYSC PM Domains
  ARM: dts: r8a7791: Add SYSC PM Domains
  ARM: dts: r8a7790: Add SYSC PM Domains
  ARM: dts: r8a7779: Add SYSC PM Domains
  soc: renesas: rcar-sysc: Add support for R-Car H3 power areas
  soc: renesas: rcar-sysc: Add support for R-Car E2 power areas
  soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas
  soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas
  soc: renesas: rcar-sysc: Add support for R-Car H2 power areas
  soc: renesas: rcar-sysc: Add support for R-Car H1 power areas
  soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices
  ARM: dts: gose: Enable SDHI controllers
  ARM: dts: r8a7793: Add SDHI controllers
  ARM: dts: r8a7790: fix max-frequency for SDHI
  ...
parents bf162006 25611e4e
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Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt 0 → 100644
View file @ 1cf257ab
DT bindings for the Renesas R-Car System Controller
== System Controller Node ==
The R-Car System Controller provides power management for the CPU cores and
various coprocessors.
Required properties:
- compatible: Must contain exactly one of the following:
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)
- "renesas,r8a7792-sysc" (R-Car V2H)
- "renesas,r8a7793-sysc" (R-Car M2-N)
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
Example:
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7791-sysc";
reg = <0 0xe6180000 0 0x0200>;
#power-domain-cells = <1>;
};
== PM Domain Consumers ==
Devices residing in a power area must refer to that power area, as documented
by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Required properties:
- power-domains: A phandle and symbolic PM domain specifier, as defined in
<dt-bindings/power/r8a77*-sysc.h>.
Example:
L2_CA15: cache-controller@0 {
compatible = "cache";
power-domains = <&sysc R8A7791_PD_CA15_SCU>;
cache-unified;
cache-level = <2>;
};
MAINTAINERS
View file @ 1cf257ab
......@@ -1491,6 +1491,8 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
S: Supported
F: arch/arm64/boot/dts/renesas/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
ARM/RISCPC ARCHITECTURE
M: Russell King <linux@arm.linux.org.uk>
......@@ -1604,6 +1606,8 @@ F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
F: drivers/sh/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
ARM/SOCFPGA ARCHITECTURE
M: Dinh Nguyen <dinguyen@opensource.altera.com>
......
arch/arm/boot/dts/emev2-kzm9d.dts
View file @ 1cf257ab
......@@ -105,8 +105,8 @@ &iic1 {
&pfc {
uart1_pins: serial@e1030000 {
renesas,groups = "uart1_ctrl", "uart1_data";
renesas,function = "uart1";
groups = "uart1_ctrl", "uart1_data";
function = "uart1";
};
};
......
arch/arm/boot/dts/r7s72100.dtsi
View file @ 1cf257ab
......@@ -37,46 +37,41 @@ clocks {
#size-cells = <1>;
/* External clocks */
extal_clk: extal_clk {
extal_clk: extal {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
clock-output-names = "extal";
};
usb_x1_clk: usb_x1_clk {
usb_x1_clk: usb_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value must be set by board */
clock-frequency = <0>;
clock-output-names = "usb_x1";
};
/* Fixed factor clocks */
b_clk: b_clk {
b_clk: b {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <3>;
clock-output-names = "b";
};
p1_clk: p1_clk {
p1_clk: p1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <6>;
clock-output-names = "p1";
};
p0_clk: p0_clk {
p0_clk: p0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R7S72100_CLK_PLL>;
clock-mult = <1>;
clock-div = <12>;
clock-output-names = "p0";
};
/* Special CPG clocks */
......
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View file @ 1cf257ab
......@@ -189,28 +189,28 @@ &cmt1 {
&pfc {
scifa0_pins: serial0 {
renesas,groups = "scifa0_data";
renesas,function = "scifa0";
groups = "scifa0_data";
function = "scifa0";
};
mmc0_pins: mmc {
renesas,groups = "mmc0_data8", "mmc0_ctrl";
renesas,function = "mmc0";
groups = "mmc0_data8", "mmc0_ctrl";
function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
keyboard_pins: keyboard {
renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
"PORT328", "PORT329";
pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",
"PORT329";
bias-pull-up;
};
};
......
arch/arm/boot/dts/r8a73a4.dtsi
View file @ 1cf257ab
......@@ -486,37 +486,32 @@ clocks {
ranges;
/* External root clocks */
extalr_clk: extalr_clk {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "extal2";
};
fsiack_clk: fsiack_clk {
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "fsibck";
};
/* Special CPG clocks */
......@@ -540,171 +535,151 @@ zb_clk: zb_clk@e6150010 {
#clock-cells = <0>;
clock-output-names = "zb";
};
sdhi0_clk: sdhi0_clk@e6150074 {
sdhi0_clk: sdhi0ck@e6150074 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150074 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sdhi0ck";
};
sdhi1_clk: sdhi1_clk@e6150078 {
sdhi1_clk: sdhi1ck@e6150078 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sdhi1ck";
};
sdhi2_clk: sdhi2_clk@e615007c {
sdhi2_clk: sdhi2ck@e615007c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615007c 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sdhi2ck";
};
mmc0_clk: mmc0_clk@e6150240 {
mmc0_clk: mmc0@e6150240 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
mmc1_clk: mmc1_clk@e6150244 {
mmc1_clk: mmc1@e6150244 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150244 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc1";
};
vclk1_clk: vclk1_clk@e6150008 {
vclk1_clk: vclk1@e6150008 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150008 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk1";
};
vclk2_clk: vclk2_clk@e615000c {
vclk2_clk: vclk2@e615000c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615000c 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk2";
};
vclk3_clk: vclk3_clk@e615001c {
vclk3_clk: vclk3@e615001c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615001c 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk3";
};
vclk4_clk: vclk4_clk@e6150014 {
vclk4_clk: vclk4@e6150014 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150014 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk4";
};
vclk5_clk: vclk5_clk@e6150034 {
vclk5_clk: vclk5@e6150034 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150034 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<0>, <&extal2_clk>, <&main_div2_clk>,
<&extalr_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "vclk5";
};
fsia_clk: fsia_clk@e6150018 {
fsia_clk: fsia@e6150018 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150018 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&fsiack_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "fsia";
};
fsib_clk: fsib_clk@e6150090 {
fsib_clk: fsib@e6150090 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150090 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&fsibck_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "fsib";
};
mp_clk: mp_clk@e6150080 {
mp_clk: mp@e6150080 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150080 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "mp";
};
m4_clk: m4_clk@e6150098 {
m4_clk: m4@e6150098 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150098 0 4>;
clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
#clock-cells = <0>;
clock-output-names = "m4";
};
hsi_clk: hsi_clk@e615026c {
hsi_clk: hsi@e615026c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615026c 0 4>;
clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
#clock-cells = <0>;
clock-output-names = "hsi";
};
spuv_clk: spuv_clk@e6150094 {
spuv_clk: spuv@e6150094 {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150094 0 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "spuv";
};
/* Fixed factor clocks */
main_div2_clk: main_div2_clk {
main_div2_clk: main_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "main_div2";
};
pll0_div2_clk: pll0_div2_clk {
pll0_div2_clk: pll0_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll0_div2";
};
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
extal1_div2_clk: extal1_div2_clk {
extal1_div2_clk: extal1_div2 {
compatible = "fixed-factor-clock";
clocks = <&extal1_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "extal1_div2";
};
/* Gate clocks */
......
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View file @ 1cf257ab
......@@ -228,44 +228,44 @@ &pfc {
pinctrl-names = "default";
ether_pins: ether {
renesas,groups = "gether_mii", "gether_int";
renesas,function = "gether";
groups = "gether_mii", "gether_int";
function = "gether";
};
scifa1_pins: serial1 {
renesas,groups = "scifa1_data";
renesas,function = "scifa1";
groups = "scifa1_data";
function = "scifa1";
};
st1232_pins: touchscreen {
renesas,groups = "intc_irq10";
renesas,function = "intc";
groups = "intc_irq10";
function = "intc";
};
backlight_pins: backlight {
renesas,groups = "tpu0_to2_1";
renesas,function = "tpu0";
groups = "tpu0_to2_1";
function = "tpu0";
};
mmc0_pins: mmc0 {
renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
renesas,function = "mmc0";
groups = "mmc0_data8_1", "mmc0_ctrl_1";
function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
function = "sdhi0";
};
fsia_pins: sounda {
renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
"fsia_data_in_1", "fsia_data_out_0";
renesas,function = "fsia";
groups = "fsia_sclk_in", "fsia_mclk_out",
"fsia_data_in_1", "fsia_data_out_0";
function = "fsia";
};
lcd0_pins: lcd0 {
renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
renesas,function = "lcd0";
groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
function = "lcd0";
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
......
arch/arm/boot/dts/r8a7740.dtsi
View file @ 1cf257ab
......@@ -422,53 +422,45 @@ clocks {
ranges;
/* External root clock */
extalr_clk: extalr_clk {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal2";
};
dv_clk: dv_clk {
dv_clk: dv {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "dv";
};
fmsick_clk: fmsick_clk {
fmsick_clk: fmsick {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fmsick";
};
fmsock_clk: fmsock_clk {
fmsock_clk: fmsock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fmsock";
};
fsiack_clk: fsiack_clk {
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsibck";
};
/* Special CPG clocks */
......@@ -486,7 +478,7 @@ cpg_clocks: cpg_clocks@e6150000 {
};
/* Variable factor clocks (DIV6) */
vclk1_clk: vclk1_clk@e6150008 {
vclk1_clk: vclk1@e6150008 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150008 4>;
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
......@@ -494,9 +486,8 @@ vclk1_clk: vclk1_clk@e6150008 {
<&extal1_div2_clk>, <&extalr_clk>, <0>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk1";
};
vclk2_clk: vclk2_clk@e615000c {
vclk2_clk: vclk2@e615000c {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615000c 4>;
clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
......@@ -504,77 +495,67 @@ vclk2_clk: vclk2_clk@e615000c {
<&extal1_div2_clk>, <&extalr_clk>, <0>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk2";
};
fmsi_clk: fmsi_clk@e6150010 {
fmsi_clk: fmsi@e6150010 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150010 4>;
clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "fmsi";
};
fmso_clk: fmso_clk@e6150014 {
fmso_clk: fmso@e6150014 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150014 4>;
clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "fmso";
};
fsia_clk: fsia_clk@e6150018 {
fsia_clk: fsia@e6150018 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150018 4>;
clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "fsia";
};
sub_clk: sub_clk@e6150080 {
sub_clk: sub@e6150080 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150080 4>;
clocks = <&pllc1_div2_clk>,
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "sub";
};
spu_clk: spu_clk@e6150084 {
spu_clk: spu@e6150084 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150084 4>;
clocks = <&pllc1_div2_clk>,
<&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "spu";
};
vou_clk: vou_clk@e6150088 {
vou_clk: vou@e6150088 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150088 4>;
clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
<0>;
#clock-cells = <0>;
clock-output-names = "vou";
};
stpro_clk: stpro_clk@e615009c {
stpro_clk: stpro@e615009c {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615009c 4>;
clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
#clock-cells = <0>;
clock-output-names = "stpro";
};
/* Fixed factor clocks */
pllc1_div2_clk: pllc1_div2_clk {
pllc1_div2_clk: pllc1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pllc1_div2";
};
extal1_div2_clk: extal1_div2_clk {
extal1_div2_clk: extal1_div2 {
compatible = "fixed-factor-clock";
clocks = <&extal1_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "extal1_div2";
};
/* Gate clocks */
......
arch/arm/boot/dts/r8a7778-bockw.dts
View file @ 1cf257ab
......@@ -130,53 +130,53 @@ &pfc {
pinctrl-names = "default";
scif0_pins: serial0 {
renesas,groups = "scif0_data_a", "scif0_ctrl";
renesas,function = "scif0";
groups = "scif0_data_a", "scif0_ctrl";
function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
mmc_pins: mmc {
renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc";
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi0_pup_pins: sd0_pup {
renesas,groups = "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
groups = "sdhi0_cd", "sdhi0_wp";
function = "sdhi0";
bias-pull-up;
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0_a";
renesas,function = "hspi0";
groups = "hspi0_a";
function = "hspi0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
vin1_pins: vin1 {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};
};
......
arch/arm/boot/dts/r8a7778.dtsi
View file @ 1cf257ab
......@@ -443,11 +443,10 @@ clocks {
ranges;
/* External input clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "extal";
};
/* External SCIF clock */
......@@ -474,59 +473,51 @@ cpg_clocks: cpg_clocks@ffc80000 {
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "audio_clk_a";
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "audio_clk_b";
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "audio_clk_c";
};
/* Fixed ratio clocks */
g_clk: g_clk {
g_clk: g {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
clock-output-names = "g";
};
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clock-output-names = "i";
};
s3_clk: s3_clk {
s3_clk: s3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "s3";
};
s4_clk: s4_clk {
s4_clk: s4 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "s4";
};
z_clk: z_clk {
z_clk: z {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clock-output-names = "z";
};
/* Gate clocks */
......
arch/arm/boot/dts/r8a7779-marzen.dts
View file @ 1cf257ab
......@@ -170,49 +170,49 @@ &pfc {
du_pins: du {
du0 {
renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
renesas,function = "du0";
groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
function = "du0";
};
du1 {
renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
renesas,function = "du1";
groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
function = "du1";
};
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk_b";
renesas,function = "scif_clk";
groups = "scif_clk_b";
function = "scif_clk";
};
ethernet_pins: ethernet {
intc {
renesas,groups = "intc_irq1_b";
renesas,function = "intc";
groups = "intc_irq1_b";
function = "intc";
};
lbsc {
renesas,groups = "lbsc_ex_cs0";
renesas,function = "lbsc";
groups = "lbsc_ex_cs0";
function = "lbsc";
};
};
scif2_pins: serial2 {
renesas,groups = "scif2_data_c";
renesas,function = "scif2";
groups = "scif2_data_c";
function = "scif2";
};
scif4_pins: serial4 {
renesas,groups = "scif4_data";
renesas,function = "scif4";
groups = "scif4_data";
function = "scif4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
function = "sdhi0";
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0";
renesas,function = "hspi0";
groups = "hspi0";
function = "hspi0";
};
};
......
arch/arm/boot/dts/r8a7779.dtsi
View file @ 1cf257ab
......@@ -14,6 +14,7 @@
#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7779-sysc.h>
/ {
compatible = "renesas,r8a7779";
......@@ -34,18 +35,21 @@ cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1000000000>;
power-domains = <&sysc R8A7779_PD_ARM1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
clock-frequency = <1000000000>;
power-domains = <&sysc R8A7779_PD_ARM2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
clock-frequency = <1000000000>;
power-domains = <&sysc R8A7779_PD_ARM3>;
};
};
......@@ -67,7 +71,7 @@ timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cpg_clocks R8A7779_CLK_ZS>;
};
......@@ -173,7 +177,7 @@ i2c0: i2c@ffc70000 {
reg = <0xffc70000 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -184,7 +188,7 @@ i2c1: i2c@ffc71000 {
reg = <0xffc71000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -195,7 +199,7 @@ i2c2: i2c@ffc72000 {
reg = <0xffc72000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -206,7 +210,7 @@ i2c3: i2c@ffc73000 {
reg = <0xffc73000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -218,7 +222,7 @@ scif0: serial@ffe40000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -230,7 +234,7 @@ scif1: serial@ffe41000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -242,7 +246,7 @@ scif2: serial@ffe42000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -254,7 +258,7 @@ scif3: serial@ffe43000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -266,7 +270,7 @@ scif4: serial@ffe44000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -278,7 +282,7 @@ scif5: serial@ffe45000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -300,7 +304,7 @@ tmu0: timer@ffd80000 {
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>;
......@@ -315,7 +319,7 @@ tmu1: timer@ffd81000 {
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>;
......@@ -330,7 +334,7 @@ tmu2: timer@ffd82000 {
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>;
......@@ -342,7 +346,7 @@ sata: sata@fc600000 {
reg = <0xfc600000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
};
sdhi0: sd@ffe4c000 {
......@@ -350,7 +354,7 @@ sdhi0: sd@ffe4c000 {
reg = <0xffe4c000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -359,7 +363,7 @@ sdhi1: sd@ffe4d000 {
reg = <0xffe4d000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -368,7 +372,7 @@ sdhi2: sd@ffe4e000 {
reg = <0xffe4e000 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -377,7 +381,7 @@ sdhi3: sd@ffe4f000 {
reg = <0xffe4f000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -388,7 +392,7 @@ hspi0: spi@fffc7000 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -399,7 +403,7 @@ hspi1: spi@fffc8000 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -410,7 +414,7 @@ hspi2: spi@fffc6000 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
};
......@@ -419,7 +423,7 @@ du: display@fff80000 {
reg = <0 0xfff80000 0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
ports {
......@@ -445,12 +449,11 @@ clocks {
ranges;
/* External root clock */
extal_clk: extal_clk {
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overriden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/* External SCIF clock */
......@@ -474,37 +477,33 @@ cpg_clocks: clocks@ffc80000 {
};
/* Fixed factor clocks */
i_clk: i_clk {
i_clk: i {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "i";
};
s3_clk: s3_clk {
s3_clk: s3 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "s3";
};
s4_clk: s4_clk {
s4_clk: s4 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <16>;
clock-mult = <1>;
clock-output-names = "s4";
};
g_clk: g_clk {
g_clk: g {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "g";
};
/* Gate clocks */
......@@ -591,4 +590,10 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
"mmc1", "mmc0";
};
};
sysc: system-controller@ffd85000 {
compatible = "renesas,r8a7779-sysc";
reg = <0xffd85000 0x0200>;
#power-domain-cells = <1>;
};
};
arch/arm/boot/dts/r8a7790-lager.dts
View file @ 1cf257ab
......@@ -176,11 +176,10 @@ vccq_sdhi2: regulator@4 {
1800000 0>;
};
audio_clock: clock {
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
......@@ -314,119 +313,133 @@ &pfc {
pinctrl-names = "default";
du_pins: du {
renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
function = "du";
};
scif0_pins: serial0 {
renesas,groups = "scif0_data";
renesas,function = "scif0";
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
scifa1_pins: serial1 {
renesas,groups = "scifa1_data";
renesas,function = "scifa1";
groups = "scifa1_data";
function = "scifa1";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
};
mmc1_pins: mmc1 {
renesas,groups = "mmc1_data8", "mmc1_ctrl";
renesas,function = "mmc1";
groups = "mmc1_data8", "mmc1_ctrl";
function = "mmc1";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
msiof1_pins: spi2 {
renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
"msiof1_tx";
renesas,function = "msiof1";
function = "msiof1";
};
i2c0_pins: i2c0 {
renesas,groups = "i2c0";
renesas,function = "i2c0";
groups = "i2c0";
function = "i2c0";
};
iic0_pins: iic0 {
renesas,groups = "iic0";
renesas,function = "iic0";
groups = "iic0";
function = "iic0";
};
iic1_pins: iic1 {
renesas,groups = "iic1";
renesas,function = "iic1";
groups = "iic1";
function = "iic1";
};
iic2_pins: iic2 {
renesas,groups = "iic2";
renesas,function = "iic2";
groups = "iic2";
function = "iic2";
};
iic3_pins: iic3 {
renesas,groups = "iic3";
renesas,function = "iic3";
groups = "iic3";
function = "iic3";
};
hsusb_pins: hsusb {
renesas,groups = "usb0_ovc_vbus";
renesas,function = "usb0";
groups = "usb0_ovc_vbus";
function = "usb0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
usb2_pins: usb2 {
renesas,groups = "usb2";
renesas,function = "usb2";
groups = "usb2";
function = "usb2";
};
vin1_pins: vin {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};
......@@ -539,21 +552,25 @@ pmic: pmic@0 {
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
status = "okay";
};
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ 1cf257ab
This diff is collapsed.
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 1cf257ab
......@@ -242,11 +242,10 @@ vccq_sdhi2: regulator@5 {
1800000 0>;
};
audio_clock: clock {
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
......@@ -324,89 +323,89 @@ &pfc {
pinctrl-names = "default";
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
groups = "i2c2";
function = "i2c2";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
groups = "scif0_data_d";
function = "scif0";
};
scif1_pins: serial1 {
renesas,groups = "scif1_data_d";
renesas,function = "scif1";
groups = "scif1_data_d";
function = "scif1";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
msiof0_pins: spi1 {
renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
"msiof0_tx";
renesas,function = "msiof0";
function = "msiof0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
vin1_pins: vin1 {
renesas,groups = "vin1_data8", "vin1_clk";
renesas,function = "vin1";
groups = "vin1_data8", "vin1_clk";
function = "vin1";
};
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};
......
arch/arm/boot/dts/r8a7791-porter.dts
View file @ 1cf257ab
......@@ -113,11 +113,10 @@ x16_clk: x16-clock {
clock-frequency = <74250000>;
};
x14_clk: x14-clock {
x14_clk: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
sound {
......@@ -147,78 +146,78 @@ &pfc {
pinctrl-names = "default";
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
groups = "scif0_data_d";
function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
groups = "i2c2";
function = "i2c2";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
can0_pins: can0 {
renesas,groups = "can0_data";
renesas,function = "can0";
groups = "can0_data";
function = "can0";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
ssi_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
audio_clk_pins: audio_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ 1cf257ab
This diff is collapsed.
arch/arm/boot/dts/r8a7793-gose.dts
View file @ 1cf257ab
......@@ -158,11 +158,82 @@ led8 {
};
};
audio_clock: clock {
vcc_sdhi0: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator@1 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi1: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator@3 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi2: regulator@4 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi2: regulator@5 {
compatible = "regulator-gpio";
regulator-name = "SDHI2 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
......@@ -240,53 +311,68 @@ &pfc {
pinctrl-names = "default";
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
groups = "i2c2";
function = "i2c2";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
groups = "scif0_data_d";
function = "scif0";
};
scif1_pins: serial1 {
renesas,groups = "scif1_data_d";
renesas,function = "scif1";
groups = "scif1_data_d";
function = "scif1";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq0";
renesas,function = "intc";
groups = "intc_irq0";
function = "intc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
groups = "audio_clk_a";
function = "audio_clk";
};
};
......@@ -329,6 +415,38 @@ &scif_clk {
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ 1cf257ab
This diff is collapsed.
arch/arm/boot/dts/r8a7794-alt.dts
View file @ 1cf257ab
......@@ -107,38 +107,38 @@ &pfc {
pinctrl-names = "default";
du_pins: du {
renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
renesas,function = "du";
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
function = "du";
};
scif2_pins: serial2 {
renesas,groups = "scif2_data";
renesas,function = "scif2";
groups = "scif2_data";
function = "scif2";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq8";
renesas,function = "intc";
groups = "intc_irq8";
function = "intc";
};
i2c1_pins: i2c1 {
renesas,groups = "i2c1";
renesas,function = "i2c1";
groups = "i2c1";
function = "i2c1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
};
......@@ -148,8 +148,8 @@ &cmt0 {
&pfc {
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
};
......
arch/arm/boot/dts/r8a7794-silk.dts
View file @ 1cf257ab
......@@ -130,58 +130,58 @@ &pfc {
pinctrl-names = "default";
scif2_pins: serial2 {
renesas,groups = "scif2_data";
renesas,function = "scif2";
groups = "scif2_data";
function = "scif2";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
groups = "scif_clk";
function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
groups = "eth_link", "eth_mdio", "eth_rmii";
function = "eth";
};
phy1_pins: phy1 {
renesas,groups = "intc_irq8";
renesas,function = "intc";
groups = "intc_irq8";
function = "intc";
};
i2c1_pins: i2c1 {
renesas,groups = "i2c1";
renesas,function = "i2c1";
groups = "i2c1";
function = "i2c1";
};
mmcif0_pins: mmcif0 {
renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc";
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
groups = "usb1";
function = "usb1";
};
};
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ 1cf257ab
This diff is collapsed.
arch/arm/boot/dts/sh73a0-kzm9g.dts
View file @ 1cf257ab
......@@ -149,6 +149,13 @@ home-key {
label = "SW1";
wakeup-source;
};
wakeup-key {
gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
label = "NMI";
wakeup-source;
};
};
sound {
......@@ -329,41 +336,41 @@ &mmcif {
&pfc {
i2c3_pins: i2c3 {
renesas,groups = "i2c3_1";
renesas,function = "i2c3";
groups = "i2c3_1";
function = "i2c3";
};
mmcif_pins: mmc {
mux {
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
renesas,function = "mmc0";
groups = "mmc0_data8_0", "mmc0_ctrl_0";
function = "mmc0";
};
cfg {
renesas,groups = "mmc0_data8_0";
renesas,pins = "PORT279";
groups = "mmc0_data8_0";
pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: serial4 {
renesas,groups = "scifa4_data", "scifa4_ctrl";
renesas,function = "scifa4";
groups = "scifa4_data", "scifa4_ctrl";
function = "scifa4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
renesas,function = "sdhi0";
groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
};
fsia_pins: sounda {
renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
"fsia_data_in", "fsia_data_out";
renesas,function = "fsia";
groups = "fsia_mclk_in", "fsia_sclk_in",
"fsia_data_in", "fsia_data_out";
function = "fsia";
};
};
......
arch/arm/boot/dts/sh73a0.dtsi
View file @ 1cf257ab
......@@ -43,7 +43,7 @@ cpu@1 {
timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&twd_clk>;
};
......@@ -602,39 +602,33 @@ clocks {
ranges;
/* External root clocks */
extalr_clk: extalr_clk {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "extalr";
};
extal1_clk: extal1_clk {
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "extal1";
};
extal2_clk: extal2_clk {
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "extal2";
};
extcki_clk: extcki_clk {
extcki_clk: extcki {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "extcki";
};
fsiack_clk: fsiack_clk {
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsiack";
};
fsibck_clk: fsibck_clk {
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "fsibck";
};
/* Special CPG clocks */
......@@ -650,7 +644,7 @@ cpg_clocks: cpg_clocks@e6150000 {
};
/* Variable factor clocks (DIV6) */
vclk1_clk: vclk1_clk@e6150008 {
vclk1_clk: vclk1@e6150008 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150008 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
......@@ -658,9 +652,8 @@ vclk1_clk: vclk1_clk@e6150008 {
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk1";
};
vclk2_clk: vclk2_clk@e615000c {
vclk2_clk: vclk2@e615000c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615000c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
......@@ -668,9 +661,8 @@ vclk2_clk: vclk2_clk@e615000c {
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk2";
};
vclk3_clk: vclk3_clk@e615001c {
vclk3_clk: vclk3@e615001c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615001c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
......@@ -678,7 +670,6 @@ vclk3_clk: vclk3_clk@e615001c {
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
<0>;
#clock-cells = <0>;
clock-output-names = "vclk3";
};
zb_clk: zb_clk@e6150010 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
......@@ -688,168 +679,148 @@ zb_clk: zb_clk@e6150010 {
#clock-cells = <0>;
clock-output-names = "zb";
};
flctl_clk: flctl_clk@e6150014 {
flctl_clk: flctlck@e6150014 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150014 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "flctlck";
};
sdhi0_clk: sdhi0_clk@e6150074 {
sdhi0_clk: sdhi0ck@e6150074 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150074 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div13_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "sdhi0ck";
};
sdhi1_clk: sdhi1_clk@e6150078 {
sdhi1_clk: sdhi1ck@e6150078 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150078 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div13_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "sdhi1ck";
};
sdhi2_clk: sdhi2_clk@e615007c {
sdhi2_clk: sdhi2ck@e615007c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615007c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div13_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "sdhi2ck";
};
fsia_clk: fsia_clk@e6150018 {
fsia_clk: fsia@e6150018 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150018 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&fsiack_clk>, <&fsiack_clk>;
#clock-cells = <0>;
clock-output-names = "fsia";
};
fsib_clk: fsib_clk@e6150090 {
fsib_clk: fsib@e6150090 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150090 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&fsibck_clk>, <&fsibck_clk>;
#clock-cells = <0>;
clock-output-names = "fsib";
};
sub_clk: sub_clk@e6150080 {
sub_clk: sub@e6150080 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150080 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "sub";
};
spua_clk: spua_clk@e6150084 {
spua_clk: spua@e6150084 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150084 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "spua";
};
spuv_clk: spuv_clk@e6150094 {
spuv_clk: spuv@e6150094 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150094 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&extal2_clk>, <&extal2_clk>;
#clock-cells = <0>;
clock-output-names = "spuv";
};
msu_clk: msu_clk@e6150088 {
msu_clk: msu@e6150088 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150088 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "msu";
};
hsi_clk: hsi_clk@e615008c {
hsi_clk: hsi@e615008c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615008c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&pll1_div7_clk>, <0>;
#clock-cells = <0>;
clock-output-names = "hsi";
};
mfg1_clk: mfg1_clk@e6150098 {
mfg1_clk: mfg1@e6150098 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150098 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "mfg1";
};
mfg2_clk: mfg2_clk@e615009c {
mfg2_clk: mfg2@e615009c {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615009c 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "mfg2";
};
dsit_clk: dsit_clk@e6150060 {
dsit_clk: dsit@e6150060 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150060 4>;
clocks = <&pll1_div2_clk>, <0>,
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
#clock-cells = <0>;
clock-output-names = "dsit";
};
dsi0p_clk: dsi0p_clk@e6150064 {
dsi0p_clk: dsi0pck@e6150064 {
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150064 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
<&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
<&extcki_clk>, <0>, <0>, <0>;
#clock-cells = <0>;
clock-output-names = "dsi0pck";
};
/* Fixed factor clocks */
main_div2_clk: main_div2_clk {
main_div2_clk: main_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "main_div2";
};
pll1_div2_clk: pll1_div2_clk {
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "pll1_div2";
};
pll1_div7_clk: pll1_div7_clk {
pll1_div7_clk: pll1_div7 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <7>;
clock-mult = <1>;
clock-output-names = "pll1_div7";
};
pll1_div13_clk: pll1_div13_clk {
pll1_div13_clk: pll1_div13 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <13>;
clock-mult = <1>;
clock-output-names = "pll1_div13";
};
twd_clk: twd_clk {
twd_clk: twd {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_Z>;
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clock-output-names = "twd";
};
/* Gate clocks */
......
arch/arm/mach-shmobile/Kconfig
View file @ 1cf257ab
......@@ -4,11 +4,6 @@ config ARCH_SHMOBILE
config ARCH_SHMOBILE_MULTI
bool
config PM_RCAR
bool
select PM
select PM_GENERIC_DOMAINS
config PM_RMOBILE
bool
select PM
......@@ -16,13 +11,15 @@ config PM_RMOBILE
config ARCH_RCAR_GEN1
bool
select PM_RCAR
select PM
select PM_GENERIC_DOMAINS
select RENESAS_INTC_IRQPIN
select SYS_SUPPORTS_SH_TMU
config ARCH_RCAR_GEN2
bool
select PM_RCAR
select PM
select PM_GENERIC_DOMAINS
select RENESAS_IRQC
select SYS_SUPPORTS_SH_CMT
select PCI_DOMAINS if PCI
......
arch/arm/mach-shmobile/Makefile
View file @ 1cf257ab
......@@ -39,7 +39,6 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
# PM objects
obj-$(CONFIG_SUSPEND) += suspend.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_PM_RCAR) += pm-rcar.o
obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
......
arch/arm/mach-shmobile/pm-r8a7779.c
View file @ 1cf257ab
......@@ -9,9 +9,10 @@
* for more details.
*/
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/io.h>
#include "pm-rcar.h"
#include "r8a7779.h"
/* SYSC */
......
arch/arm/mach-shmobile/pm-rcar-gen2.c
View file @ 1cf257ab
......@@ -13,9 +13,9 @@
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/smp.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/io.h>
#include "common.h"
#include "pm-rcar.h"
#include "rcar-gen2.h"
/* RST */
......
arch/arm/mach-shmobile/smp-r8a7779.c
View file @ 1cf257ab
......@@ -19,13 +19,13 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "common.h"
#include "pm-rcar.h"
#include "r8a7779.h"
#define AVECR IOMEM(0xfe700040)
......
arch/arm/mach-shmobile/smp-r8a7790.c
View file @ 1cf257ab
......@@ -17,12 +17,12 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/smp_plat.h>
#include "common.h"
#include "platsmp-apmu.h"
#include "pm-rcar.h"
#include "rcar-gen2.h"
#include "r8a7790.h"
......
drivers/clk/Kconfig
View file @ 1cf257ab
......@@ -201,6 +201,7 @@ source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/samsung/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
......
drivers/clk/renesas/Kconfig 0 → 100644
View file @ 1cf257ab
config CLK_RENESAS_CPG_MSSR
bool
default y if ARCH_R8A7795
config CLK_RENESAS_CPG_MSTP
bool
default y if ARCH_R7S72100
default y if ARCH_R8A73A4
default y if ARCH_R8A7740
default y if ARCH_R8A7778
default y if ARCH_R8A7779
default y if ARCH_R8A7790
default y if ARCH_R8A7791
default y if ARCH_R8A7793
default y if ARCH_R8A7794
default y if ARCH_SH73A0
drivers/clk/renesas/Makefile
View file @ 1cf257ab
obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
r8a7795-cpg-mssr.o clk-div6.o
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
drivers/clk/renesas/clk-mstp.c
View file @ 1cf257ab
......@@ -243,9 +243,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
}
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
{
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
......@@ -297,7 +295,7 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
return error;
}
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!list_empty(&dev->power.subsys_data->clock_list))
pm_clk_destroy(dev);
......@@ -326,4 +324,3 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
of_genpd_add_provider_simple(np, pd);
}
#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
drivers/clk/renesas/r8a7795-cpg-mssr.c
View file @ 1cf257ab
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drivers/clk/renesas/renesas-cpg-mssr.c
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drivers/clk/renesas/renesas-cpg-mssr.h
View file @ 1cf257ab
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drivers/soc/Makefile
View file @ 1cf257ab
This diff is collapsed.
drivers/soc/renesas/Makefile 0 → 100644
View file @ 1cf257ab
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drivers/soc/renesas/r8a7779-sysc.c 0 → 100644
View file @ 1cf257ab
This diff is collapsed.
drivers/soc/renesas/r8a7790-sysc.c 0 → 100644
View file @ 1cf257ab
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drivers/soc/renesas/r8a7791-sysc.c 0 → 100644
View file @ 1cf257ab
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drivers/soc/renesas/r8a7794-sysc.c 0 → 100644
View file @ 1cf257ab
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drivers/soc/renesas/r8a7795-sysc.c 0 → 100644
View file @ 1cf257ab
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drivers/soc/renesas/rcar-sysc.h 0 → 100644
View file @ 1cf257ab
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include/dt-bindings/clock/r8a7790-clock.h
View file @ 1cf257ab
This diff is collapsed.
include/dt-bindings/clock/r8a7794-clock.h
View file @ 1cf257ab
This diff is collapsed.
include/dt-bindings/power/r8a7779-sysc.h 0 → 100644
View file @ 1cf257ab
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include/dt-bindings/power/r8a7790-sysc.h 0 → 100644
View file @ 1cf257ab
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include/dt-bindings/power/r8a7791-sysc.h 0 → 100644
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include/dt-bindings/power/r8a7793-sysc.h 0 → 100644
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include/dt-bindings/power/r8a7794-sysc.h 0 → 100644
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include/dt-bindings/power/r8a7795-sysc.h 0 → 100644
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include/linux/clk/renesas.h
View file @ 1cf257ab
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