Commit 1df67a4e authored by James Zhu's avatar James Zhu Committed by Alex Deucher

Revert "drm/amdgpu/vcn3.0: remove extra asic type check"

This reverts commit 058c07201ec7d373fc6a0a570b38a8a9d62c29fb.
Chip NAVY_FLOUNDER uses vcn3.0, but it has only one VCN instance.
Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ea368183
...@@ -88,20 +88,23 @@ static int vcn_v3_0_early_init(void *handle) ...@@ -88,20 +88,23 @@ static int vcn_v3_0_early_init(void *handle)
adev->vcn.num_enc_rings = 1; adev->vcn.num_enc_rings = 1;
} else { } else {
u32 harvest; if (adev->asic_type == CHIP_SIENNA_CICHLID) {
int i; u32 harvest;
int i;
adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
for (i = 0; i < adev->vcn.num_vcn_inst; i++) { adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
adev->vcn.harvest_config |= 1 << i; if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
} adev->vcn.harvest_config |= 1 << i;
}
if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
AMDGPU_VCN_HARVEST_VCN1)) AMDGPU_VCN_HARVEST_VCN1))
/* both instances are harvested, disable the block */ /* both instances are harvested, disable the block */
return -ENOENT; return -ENOENT;
} else
adev->vcn.num_vcn_inst = 1;
adev->vcn.num_enc_rings = 2; adev->vcn.num_enc_rings = 2;
} }
......
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