Commit 1e5ac602 authored by Phil Edworthy's avatar Phil Edworthy Committed by Greg Kroah-Hartman

clk: renesas: r9a06g032: Fix UART34567 clock rate

[ Upstream commit ee02950d ]

The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through
7 is UART34567.
For UART012, we stop the clock driver from changing the clock rate. This
is because the Synopsys UART driver simply sets the reference clock to 16x
the baud rate, but doesn't check if the actual rate is within the required
tolerance. The RZ/N1 clock divider can't provide this (we have to rely on
the UART's internal divider to set the correct clock rate), so you end up
with a clock rate that is way off what you wanted.

In addition, since the clock is shared between multiple UARTs, you don't
want the driver trying to change the clock rate as it may affect the other
UARTs (which may not have been configured yet, so you don't know what baud
rate they will use). Normally, the clock rate is set early on before Linux
to some very high rate that supports all of the clock rates you want.

This change stops the UART34567 clock rate from changing for the same
reasons.
Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Fixes: 4c3d8852 ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent a178c7ab
...@@ -539,7 +539,8 @@ r9a06g032_div_round_rate(struct clk_hw *hw, ...@@ -539,7 +539,8 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
* several uarts attached to this divider, and changing this impacts * several uarts attached to this divider, and changing this impacts
* everyone. * everyone.
*/ */
if (clk->index == R9A06G032_DIV_UART) { if (clk->index == R9A06G032_DIV_UART ||
clk->index == R9A06G032_DIV_P2_PG) {
pr_devel("%s div uart hack!\n", __func__); pr_devel("%s div uart hack!\n", __func__);
return clk_get_rate(hw->clk); return clk_get_rate(hw->clk);
} }
......
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