Commit 1f06dee8 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amdgpu: Enable/disable gfx PG feature in rlc safe mode

This is required by gfx hw and can fix the rlc hang when
do s3 stree test on Cz/St.
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarHang Zhou <hang.zhou@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 43370c4c
...@@ -5660,6 +5660,11 @@ static int gfx_v8_0_set_powergating_state(void *handle, ...@@ -5660,6 +5660,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
AMD_PG_SUPPORT_RLC_SMU_HS |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_GFX_DMG))
adev->gfx.rlc.funcs->enter_safe_mode(adev);
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_CARRIZO: case CHIP_CARRIZO:
case CHIP_STONEY: case CHIP_STONEY:
...@@ -5709,7 +5714,11 @@ static int gfx_v8_0_set_powergating_state(void *handle, ...@@ -5709,7 +5714,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
default: default:
break; break;
} }
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
AMD_PG_SUPPORT_RLC_SMU_HS |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_GFX_DMG))
adev->gfx.rlc.funcs->exit_safe_mode(adev);
return 0; return 0;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment