Commit 1f588aeb authored by Rodrigo Vivi's avatar Rodrigo Vivi

drm/i915/cnl: Fix RMW on ddi vswing sequence.

Paulo noticed that we were missing few bits clear
before writing values back to the register on
these RMW MMIO operations.

v2: Remove "POST_" from CURSOR_COEFF_MASK. (Paulo).
v3: Remove unnecessary braces. (Jani).

Fixes: cf54ca8b ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com
parent 93e5f0b6
...@@ -1764,8 +1764,11 @@ enum skl_disp_power_wells { ...@@ -1764,8 +1764,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW2_LN0_AE, \ _CNL_PORT_TX_DW2_LN0_AE, \
_CNL_PORT_TX_DW2_LN0_F) _CNL_PORT_TX_DW2_LN0_F)
#define SWING_SEL_UPPER(x) ((x >> 3) << 15) #define SWING_SEL_UPPER(x) ((x >> 3) << 15)
#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) ((x & 0x7) << 11) #define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
#define SWING_SEL_LOWER_MASK (0x7 << 11)
#define RCOMP_SCALAR(x) ((x) << 0) #define RCOMP_SCALAR(x) ((x) << 0)
#define RCOMP_SCALAR_MASK (0xFF << 0)
#define _CNL_PORT_TX_DW4_GRP_AE 0x162350 #define _CNL_PORT_TX_DW4_GRP_AE 0x162350
#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0 #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
...@@ -1795,8 +1798,11 @@ enum skl_disp_power_wells { ...@@ -1795,8 +1798,11 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW4_LN0_F) _CNL_PORT_TX_DW4_LN0_F)
#define LOADGEN_SELECT (1 << 31) #define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12) #define POST_CURSOR_1(x) ((x) << 12)
#define POST_CURSOR_1_MASK (0x3F << 12)
#define POST_CURSOR_2(x) ((x) << 6) #define POST_CURSOR_2(x) ((x) << 6)
#define POST_CURSOR_2_MASK (0x3F << 6)
#define CURSOR_COEFF(x) ((x) << 0) #define CURSOR_COEFF(x) ((x) << 0)
#define CURSOR_COEFF_MASK (0x3F << 6)
#define _CNL_PORT_TX_DW5_GRP_AE 0x162354 #define _CNL_PORT_TX_DW5_GRP_AE 0x162354
#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4 #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
...@@ -1825,7 +1831,9 @@ enum skl_disp_power_wells { ...@@ -1825,7 +1831,9 @@ enum skl_disp_power_wells {
#define TX_TRAINING_EN (1 << 31) #define TX_TRAINING_EN (1 << 31)
#define TAP3_DISABLE (1 << 29) #define TAP3_DISABLE (1 << 29)
#define SCALING_MODE_SEL(x) ((x) << 18) #define SCALING_MODE_SEL(x) ((x) << 18)
#define SCALING_MODE_SEL_MASK (0x7 << 18)
#define RTERM_SELECT(x) ((x) << 3) #define RTERM_SELECT(x) ((x) << 3)
#define RTERM_SELECT_MASK (0x7 << 3)
#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
...@@ -1852,6 +1860,7 @@ enum skl_disp_power_wells { ...@@ -1852,6 +1860,7 @@ enum skl_disp_power_wells {
_CNL_PORT_TX_DW7_LN0_AE, \ _CNL_PORT_TX_DW7_LN0_AE, \
_CNL_PORT_TX_DW7_LN0_F) _CNL_PORT_TX_DW7_LN0_F)
#define N_SCALAR(x) ((x) << 24) #define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
/* The spec defines this only for BXT PHY0, but lets assume that this /* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel. * would exist for PHY1 too if it had a second channel.
......
...@@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, ...@@ -1813,11 +1813,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
val &= ~SCALING_MODE_SEL_MASK;
val |= SCALING_MODE_SEL(2); val |= SCALING_MODE_SEL(2);
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */ /* Program PORT_TX_DW2 */
val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Rcomp scalar is fixed as 0x98 for every table entry */ /* Rcomp scalar is fixed as 0x98 for every table entry */
...@@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, ...@@ -1828,6 +1831,8 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* We cannot write to GRP. It would overrite individual loadgen */ /* We cannot write to GRP. It would overrite individual loadgen */
for (ln = 0; ln < 4; ln++) { for (ln = 0; ln < 4; ln++) {
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
...@@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, ...@@ -1837,12 +1842,14 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
/* Program PORT_TX_DW5 */ /* Program PORT_TX_DW5 */
/* All DW5 values are fixed for every table entry */ /* All DW5 values are fixed for every table entry */
val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
val &= ~RTERM_SELECT_MASK;
val |= RTERM_SELECT(6); val |= RTERM_SELECT(6);
val |= TAP3_DISABLE; val |= TAP3_DISABLE;
I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW7 */ /* Program PORT_TX_DW7 */
val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
} }
......
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