Commit 1f7c5e4f authored by Ilia Mirkin's avatar Ilia Mirkin Committed by Sasha Levin

drm/nouveau/nv1a,nv1f/disp: fix memory clock rate retrieval

[ Upstream commit 24bf7ae3 ]

Based on the xf86-video-nv code, NFORCE (NV1A) and NFORCE2 (NV1F) have a
different way of retrieving clocks. See the
nv_hw.c:nForceUpdateArbitrationSettings function in the original code
for how these clocks were accessed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54587
Cc: stable@vger.kernel.org
Signed-off-by: default avatarIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
parent c59ef58e
...@@ -222,6 +222,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) ...@@ -222,6 +222,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
uint32_t mpllP; uint32_t mpllP;
pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
mpllP = (mpllP >> 8) & 0xf;
if (!mpllP) if (!mpllP)
mpllP = 4; mpllP = 4;
...@@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) ...@@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
uint32_t clock; uint32_t clock;
pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
return clock; return clock / 1000;
} }
ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
......
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