[ARM] spelling fixes for arm

Patch from Steven Cole.

Here are some spelling fixes for arm.
This was diffed against the current 2.5 tree.

arch/arm/kernel/process.c

@@ -2,7 +2,7 @@
  *  linux/arch/arm/kernel/process.c
  *
  *  Copyright (C) 1996-2000 Russell King - Converted to ARM.
- *  Origional Copyright (C) 1995  Linus Torvalds
+ *  Original Copyright (C) 1995  Linus Torvalds
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as

arch/arm/mach-iop3xx/iq80310-time.c

@@ -101,7 +101,7 @@ static void iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	 *
 	 * Since the timer interrupt is cascaded through the CPLD and
 	 * the 80312 and the demux code calls do_IRQ, the irq count is
-	 * going to be atleast 2 when we get here and this will cause the
+	 * going to be at least 2 when we get here and this will cause the
 	 * kernel to increment the system tick counter even if we're
 	 * idle. This causes it to look like there's always 100% system
 	 * time, which is not the case.  To get around it, we just decrement

arch/arm/mach-iop3xx/mm-321.c

 /*
  * linux/arch/arm/mach-iop3xx/mm.c
  *
- * Low level memory intialization for IOP321 based systems
+ * Low level memory initialization for IOP321 based systems
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt

arch/arm/mach-pxa/generic.c

@@ -13,7 +13,7 @@
  *
  * Since this file should be linked before any other machine specific file,
  * the __initcall() here will be executed first.  This serves as default
- * initialization stuff for PXA machines which can be overriden later if
+ * initialization stuff for PXA machines which can be overridden later if
  * need be.
  */
 #include <linux/config.h>

arch/arm/mach-pxa/sleep.S

@@ -95,7 +95,7 @@ ENTRY(pxa_cpu_suspend)
  *       This is to allow sleep_save_sp to be accessed with a relative load
  *       while we can't rely on any MMU translation.  We could have put
  *       sleep_save_sp in the .text section as well, but some setups might
- *       insist on it to be truely read-only.
+ *       insist on it to be truly read-only.
  */
 
 	.data

arch/arm/mach-sa1100/sleep.S

@@ -171,7 +171,7 @@ sa1110_sdram_controller_fix:
  *       This is to allow sleep_save_sp to be accessed with a relative load
  *       while we can't rely on any MMU translation.  We could have put
  *       sleep_save_sp in the .text section as well, but some setups might
- *       insist on it to be truely read-only.
+ *       insist on it to be truly read-only.
  */
 
 	.data

arch/arm/mm/discontig.c

@@ -20,7 +20,7 @@
 #endif
 
 /*
- * Our node_data structure for discontigous memory.
+ * Our node_data structure for discontiguous memory.
  */
 
 static bootmem_data_t node_bootmem_data[NR_NODES];

include/asm-arm/arch-adifcc/time.h

@@ -4,6 +4,6 @@
  */
 
 /*
- * No on board timer, implemenation @ arch/arm/kernel/xscale-time.c
+ * No on board timer, implementation @ arch/arm/kernel/xscale-time.c
  */
 

include/asm-arm/arch-clps711x/memory.h

@@ -95,7 +95,7 @@
  * Because of the wide memory address space between physical RAM banks on the 
  * SA1100, it's much more convenient to use Linux's NUMA support to implement
  * our memory map representation.  Assuming all memory nodes have equal access 
- * characteristics, we then have generic discontigous memory support.
+ * characteristics, we then have generic discontiguous memory support.
  *
  * Of course, all this isn't mandatory for SA1100 implementations with only
  * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.

include/asm-arm/arch-epxa10db/ether00.h

@@ -55,7 +55,7 @@ typedef struct buf_desc
 #define ETHER_ARC_SIZE         (21)
 
 /*
-*	Regsiter definitions and masks
+*	Register definitions and masks
 */
 #define ETHER_DMA_CTL(base)							(ETHER00_TYPE (base + 0x100))
 #define ETHER_DMA_CTL_DMBURST_OFST				(2)

include/asm-arm/arch-epxa10db/pld_conf00.h

@@ -8,7 +8,7 @@
 /*
  *  
  *  This file contains the register definitions for the Excalibur
- *  Interrupnt controller INT_CTRL00.
+ *  Interrupt controller INT_CTRL00.
  *
  *  Copyright (C) 2001 Altera Corporation
  *

include/asm-arm/arch-integrator/bits.h

@@ -16,7 +16,7 @@
 /* DO NOT EDIT!! - this file automatically generated
  *                 from .s file by awk -f s2h.awk
  */
-/*  Bit field defintions
+/*  Bit field definitions
  *  Copyright (C) ARM Limited 1998. All rights reserved.
  */
 

include/asm-arm/arch-iop3xx/iop310.h

 /*
  * linux/include/asm/arch-iop3xx/iop310.h
  *
- * Intel IOP310 Compainion Chip definitions
+ * Intel IOP310 Companion Chip definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as

include/asm-arm/arch-pxa/pxa-regs.h

@@ -690,9 +690,9 @@ typedef void            (*ExcpHndlr) (void) ;
 #define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
 #define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */
 
-#define ICCR0_AME       (1 << 7)           /* Adress match enable */
+#define ICCR0_AME       (1 << 7)           /* Address match enable */
 #define ICCR0_TIE       (1 << 6)           /* Transmit FIFO interrupt enable */
-#define ICCR0_RIE       (1 << 5)           /* Recieve FIFO interrupt enable */
+#define ICCR0_RIE       (1 << 5)           /* Receive FIFO interrupt enable */
 #define ICCR0_RXE       (1 << 4)           /* Receive enable */
 #define ICCR0_TXE       (1 << 3)           /* Transmit enable */
 #define ICCR0_TUS       (1 << 2)           /* Transmit FIFO underrun select */

include/asm-arm/arch-sa1100/graphicsclient.h

@@ -63,7 +63,7 @@
 #define _ADS_UARTC		0x10140000	/* UART C */
 #define _ADS_UARTD		0x10160000	/* UART D */
 
-/* UART controll lines GPIOs */
+/* UART control lines GPIOs */
 #define GPIO_GC_UART0_RTS       GPIO_GPIO15
 #define GPIO_GC_UART1_RTS	    GPIO_GPIO17
 #define GPIO_GC_UART2_RTS	    GPIO_GPIO19
@@ -71,7 +71,7 @@
 #define GPIO_GC_UART1_CTS       GPIO_GPIO16
 #define GPIO_GC_UART2_CTS       GPIO_GPIO17
 
-/* UART controll lines IRQs */
+/* UART control lines IRQs */
 #define IRQ_GC_UART0_CTS       IRQ_GPIO14
 #define IRQ_GC_UART1_CTS       IRQ_GPIO16
 #define IRQ_GC_UART2_CTS       IRQ_GPIO17

include/asm-arm/arch-sa1100/h3600_gpio.h

@@ -480,7 +480,7 @@
 #define _H3800_ASIC1_GPIO_State         0x40    /* R   See masks below  (default 0)         */
 #define _H3800_ASIC1_GPIO_Reset         0x42    /* R/W See masks below  (default 0x04)      */
 #define _H3800_ASIC1_GPIO_SleepMask     0x44    /* R/W 0:don't mask, 1:mask trigger in sleep mode  */
-#define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:ouput in sleep mode    */
+#define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:output in sleep mode    */
 #define _H3800_ASIC1_GPIO_SleepOut      0x48    /* R/W level 0:low, 1:high in sleep mode           */
 #define _H3800_ASIC1_GPIO_Status        0x4A    /* R   Pin status                                  */
 #define _H3800_ASIC1_GPIO_BattFaultDir  0x4C    /* R/W direction 0:input, 1:output in batt_fault   */

include/asm-arm/arch-sa1100/memory.h

@@ -60,7 +60,7 @@
  * Because of the wide memory address space between physical RAM banks on the 
  * SA1100, it's much convenient to use Linux's NUMA support to implement our 
  * memory map representation.  Assuming all memory nodes have equal access 
- * characteristics, we then have generic discontigous memory support.
+ * characteristics, we then have generic discontiguous memory support.
  *
  * Of course, all this isn't mandatory for SA1100 implementations with only
  * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.

include/asm-arm/arch-sa1100/uncompress.h

@@ -32,7 +32,7 @@ static void puts( const char *s )
 	} while (0);
 
 	for (; *s; s++) {
-		/* wait for space in the UART's transmiter */
+		/* wait for space in the UART's transmitter */
 		while (!(UART(UTSR1) & UTSR1_TNF));
 
 		/* send the character out. */

include/asm-arm/dma-mapping.h

@@ -182,7 +182,7 @@ dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
  * @dir: DMA transfer direction
  *
  * Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
+ * mode for DMA.  This is the scatter-gather version of the
  * above pci_map_single interface.  Here the scatter gather list
  * elements are each tagged with the appropriate dma address
  * and length.  They are obtained via sg_dma_{address,length}(SG).

include/asm-arm/proc-armo/pgalloc.h

@@ -37,7 +37,7 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 
 /*
  * We use the old 2.5.5-rmk1 hack for this.
- * This is not truely correct, but should be functional.
+ * This is not truly correct, but should be functional.
  */
 #define pte_alloc_one(mm,addr)	((struct page *)pte_alloc_one_kernel(mm,addr))
 #define pte_free(pte)		pte_free_kernel((pte_t *)pte)

include/asm-arm/sizes.h

@@ -16,7 +16,7 @@
 /* DO NOT EDIT!! - this file automatically generated
  *                 from .s file by awk -f s2h.awk
  */
-/*  Size defintions
+/*  Size definitions
  *  Copyright (C) ARM Limited 1998. All rights reserved.
  */