Commit 21038b09 authored by Bart Van Assche's avatar Bart Van Assche Committed by Martin K. Petersen

scsi: qla2xxx: Fix endianness annotations in header files

Annotate members of FC protocol and firmware dump data structures as big
endian. Annotate members of RISC control structures as little endian.
Annotate mailbox registers as little endian. Annotate the mb[] arrays as
CPU-endian because communication of the mb[] values with the hardware
happens through the readw() and writew() functions. readw() converts from
__le16 to u16 and writew() converts from u16 to __le16. Annotate 'handles'
as CPU-endian because for the firmware these are opaque values.

Link: https://lore.kernel.org/r/20200518211712.11395-15-bvanassche@acm.org
CC: Hannes Reinecke <hare@suse.de>
Cc: Nilesh Javali <njavali@marvell.com>
Cc: Quinn Tran <qutran@marvell.com>
Cc: Martin Wilck <mwilck@suse.com>
Cc: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: default avatarDaniel Wagner <dwagner@suse.de>
Reviewed-by: default avatarHimanshu Madhani <himanshu.madhani@oracle.com>
Signed-off-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 2a4b684a
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...@@ -40,7 +40,7 @@ qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds) ...@@ -40,7 +40,7 @@ qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds)
* register value. * register value.
*/ */
static __inline__ uint16_t static __inline__ uint16_t
qla2x00_debounce_register(volatile uint16_t __iomem *addr) qla2x00_debounce_register(volatile __le16 __iomem *addr)
{ {
volatile uint16_t first; volatile uint16_t first;
volatile uint16_t second; volatile uint16_t second;
......
...@@ -96,7 +96,7 @@ struct tsk_mgmt_entry_fx00 { ...@@ -96,7 +96,7 @@ struct tsk_mgmt_entry_fx00 {
uint8_t sys_define; uint8_t sys_define;
uint8_t entry_status; /* Entry Status. */ uint8_t entry_status; /* Entry Status. */
__le32 handle; /* System handle. */ uint32_t handle; /* System handle. */
uint32_t reserved_0; uint32_t reserved_0;
...@@ -121,13 +121,13 @@ struct abort_iocb_entry_fx00 { ...@@ -121,13 +121,13 @@ struct abort_iocb_entry_fx00 {
uint8_t sys_define; /* System defined. */ uint8_t sys_define; /* System defined. */
uint8_t entry_status; /* Entry Status. */ uint8_t entry_status; /* Entry Status. */
__le32 handle; /* System handle. */ uint32_t handle; /* System handle. */
__le32 reserved_0; __le32 reserved_0;
__le16 tgt_id_sts; /* Completion status. */ __le16 tgt_id_sts; /* Completion status. */
__le16 options; __le16 options;
__le32 abort_handle; /* System handle. */ uint32_t abort_handle; /* System handle. */
__le32 reserved_2; __le32 reserved_2;
__le16 req_que_no; __le16 req_que_no;
...@@ -166,7 +166,7 @@ struct fxdisc_entry_fx00 { ...@@ -166,7 +166,7 @@ struct fxdisc_entry_fx00 {
uint8_t sys_define; /* System Defined. */ uint8_t sys_define; /* System Defined. */
uint8_t entry_status; /* Entry Status. */ uint8_t entry_status; /* Entry Status. */
__le32 handle; /* System handle. */ uint32_t handle; /* System handle. */
__le32 reserved_0; /* System handle. */ __le32 reserved_0; /* System handle. */
__le16 func_num; __le16 func_num;
......
...@@ -48,26 +48,26 @@ struct cmd_nvme { ...@@ -48,26 +48,26 @@ struct cmd_nvme {
uint8_t entry_status; /* Entry Status. */ uint8_t entry_status; /* Entry Status. */
uint32_t handle; /* System handle. */ uint32_t handle; /* System handle. */
uint16_t nport_handle; /* N_PORT handle. */ __le16 nport_handle; /* N_PORT handle. */
uint16_t timeout; /* Command timeout. */ __le16 timeout; /* Command timeout. */
uint16_t dseg_count; /* Data segment count. */ __le16 dseg_count; /* Data segment count. */
uint16_t nvme_rsp_dsd_len; /* NVMe RSP DSD length */ __le16 nvme_rsp_dsd_len; /* NVMe RSP DSD length */
uint64_t rsvd; uint64_t rsvd;
uint16_t control_flags; /* Control Flags */ __le16 control_flags; /* Control Flags */
#define CF_NVME_FIRST_BURST_ENABLE BIT_11 #define CF_NVME_FIRST_BURST_ENABLE BIT_11
#define CF_DIF_SEG_DESCR_ENABLE BIT_3 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
#define CF_DATA_SEG_DESCR_ENABLE BIT_2 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
#define CF_READ_DATA BIT_1 #define CF_READ_DATA BIT_1
#define CF_WRITE_DATA BIT_0 #define CF_WRITE_DATA BIT_0
uint16_t nvme_cmnd_dseg_len; /* Data segment length. */ __le16 nvme_cmnd_dseg_len; /* Data segment length. */
__le64 nvme_cmnd_dseg_address __packed;/* Data segment address. */ __le64 nvme_cmnd_dseg_address __packed;/* Data segment address. */
__le64 nvme_rsp_dseg_address __packed; /* Data segment address. */ __le64 nvme_rsp_dseg_address __packed; /* Data segment address. */
uint32_t byte_count; /* Total byte count. */ __le32 byte_count; /* Total byte count. */
uint8_t port_id[3]; /* PortID of destination port. */ uint8_t port_id[3]; /* PortID of destination port. */
uint8_t vp_index; uint8_t vp_index;
...@@ -82,24 +82,24 @@ struct pt_ls4_request { ...@@ -82,24 +82,24 @@ struct pt_ls4_request {
uint8_t sys_define; uint8_t sys_define;
uint8_t entry_status; uint8_t entry_status;
uint32_t handle; uint32_t handle;
uint16_t status; __le16 status;
uint16_t nport_handle; __le16 nport_handle;
uint16_t tx_dseg_count; __le16 tx_dseg_count;
uint8_t vp_index; uint8_t vp_index;
uint8_t rsvd; uint8_t rsvd;
uint16_t timeout; __le16 timeout;
uint16_t control_flags; __le16 control_flags;
#define CF_LS4_SHIFT 13 #define CF_LS4_SHIFT 13
#define CF_LS4_ORIGINATOR 0 #define CF_LS4_ORIGINATOR 0
#define CF_LS4_RESPONDER 1 #define CF_LS4_RESPONDER 1
#define CF_LS4_RESPONDER_TERM 2 #define CF_LS4_RESPONDER_TERM 2
uint16_t rx_dseg_count; __le16 rx_dseg_count;
uint16_t rsvd2; __le16 rsvd2;
uint32_t exchange_address; __le32 exchange_address;
uint32_t rsvd3; __le32 rsvd3;
uint32_t rx_byte_count; __le32 rx_byte_count;
uint32_t tx_byte_count; __le32 tx_byte_count;
struct dsd64 dsd[2]; struct dsd64 dsd[2];
}; };
...@@ -107,32 +107,32 @@ struct pt_ls4_request { ...@@ -107,32 +107,32 @@ struct pt_ls4_request {
struct pt_ls4_rx_unsol { struct pt_ls4_rx_unsol {
uint8_t entry_type; uint8_t entry_type;
uint8_t entry_count; uint8_t entry_count;
uint16_t rsvd0; __le16 rsvd0;
uint16_t rsvd1; __le16 rsvd1;
uint8_t vp_index; uint8_t vp_index;
uint8_t rsvd2; uint8_t rsvd2;
uint16_t rsvd3; __le16 rsvd3;
uint16_t nport_handle; __le16 nport_handle;
uint16_t frame_size; __le16 frame_size;
uint16_t rsvd4; __le16 rsvd4;
uint32_t exchange_address; __le32 exchange_address;
uint8_t d_id[3]; uint8_t d_id[3];
uint8_t r_ctl; uint8_t r_ctl;
be_id_t s_id; be_id_t s_id;
uint8_t cs_ctl; uint8_t cs_ctl;
uint8_t f_ctl[3]; uint8_t f_ctl[3];
uint8_t type; uint8_t type;
uint16_t seq_cnt; __le16 seq_cnt;
uint8_t df_ctl; uint8_t df_ctl;
uint8_t seq_id; uint8_t seq_id;
uint16_t rx_id; __le16 rx_id;
uint16_t ox_id; __le16 ox_id;
uint32_t param; __le32 param;
uint32_t desc0; __le32 desc0;
#define PT_LS4_PAYLOAD_OFFSET 0x2c #define PT_LS4_PAYLOAD_OFFSET 0x2c
#define PT_LS4_FIRST_PACKET_LEN 20 #define PT_LS4_FIRST_PACKET_LEN 20
uint32_t desc_len; __le32 desc_len;
uint32_t payload[3]; __le32 payload[3];
}; };
/* /*
......
...@@ -800,16 +800,16 @@ struct qla82xx_legacy_intr_set { ...@@ -800,16 +800,16 @@ struct qla82xx_legacy_intr_set {
#define QLA82XX_URI_FIRMWARE_IDX_OFF 29 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29
struct qla82xx_uri_table_desc{ struct qla82xx_uri_table_desc{
uint32_t findex; __le32 findex;
uint32_t num_entries; __le32 num_entries;
uint32_t entry_size; __le32 entry_size;
uint32_t reserved[5]; __le32 reserved[5];
}; };
struct qla82xx_uri_data_desc{ struct qla82xx_uri_data_desc{
uint32_t findex; __le32 findex;
uint32_t size; __le32 size;
uint32_t reserved[5]; __le32 reserved[5];
}; };
/* UNIFIED ROMIMAGE END */ /* UNIFIED ROMIMAGE END */
...@@ -829,22 +829,22 @@ struct qla82xx_uri_data_desc{ ...@@ -829,22 +829,22 @@ struct qla82xx_uri_data_desc{
* ISP 8021 I/O Register Set structure definitions. * ISP 8021 I/O Register Set structure definitions.
*/ */
struct device_reg_82xx { struct device_reg_82xx {
uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */ __le32 req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */ __le32 rsp_q_in[64]; /* Response Queue In-Pointer. */
uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */ __le32 rsp_q_out[64]; /* Response Queue Out-Pointer. */
uint16_t mailbox_in[32]; /* Mail box In registers */ __le16 mailbox_in[32]; /* Mailbox In registers */
uint16_t unused_1[32]; __le16 unused_1[32];
uint32_t hint; /* Host interrupt register */ __le32 hint; /* Host interrupt register */
#define HINT_MBX_INT_PENDING BIT_0 #define HINT_MBX_INT_PENDING BIT_0
uint16_t unused_2[62]; __le16 unused_2[62];
uint16_t mailbox_out[32]; /* Mail box Out registers */ __le16 mailbox_out[32]; /* Mailbox Out registers */
uint32_t unused_3[48]; __le32 unused_3[48];
uint32_t host_status; /* host status */ __le32 host_status; /* host status */
#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
uint32_t host_int; /* Interrupt status. */ __le32 host_int; /* Interrupt status. */
#define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */ #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
}; };
......
This diff is collapsed.
...@@ -27,7 +27,7 @@ struct __packed qla27xx_fwdt_template { ...@@ -27,7 +27,7 @@ struct __packed qla27xx_fwdt_template {
uint32_t saved_state[16]; uint32_t saved_state[16];
uint32_t reserved_3[8]; uint32_t reserved_3[8];
uint32_t firmware_version[5]; __le32 firmware_version[5];
}; };
#define TEMPLATE_TYPE_FWDUMP 99 #define TEMPLATE_TYPE_FWDUMP 99
......
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