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Commit 2127435e authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
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[MIPS] JMR3927 cleanup 

* Kill dead codes
* Rearrange irq chip handlers
* Minimize defconfig
Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 252161ec
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Showing with 145 additions and 1227 deletions
arch/mips/Kconfig
View file @ 2127435e
...@@ -779,6 +779,7 @@ config TOSHIBA_JMR3927 ...@@ -779,6 +779,7 @@ config TOSHIBA_JMR3927
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
select TOSHIBA_BOARDS select TOSHIBA_BOARDS
select GENERIC_HARDIRQS_NO__DO_IRQ
config TOSHIBA_RBTX4927 config TOSHIBA_RBTX4927
bool "Toshiba TBTX49[23]7 board" bool "Toshiba TBTX49[23]7 board"
......
arch/mips/configs/jmr3927_defconfig
View file @ 2127435e
This diff is collapsed.
arch/mips/jmr3927/common/prom.c
View file @ 2127435e
...@@ -41,16 +41,6 @@ ...@@ -41,16 +41,6 @@
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
extern int prom_argc;
extern char **prom_argv, **prom_envp;
typedef struct
{
char *name;
/* char *val; */
}t_env_var;
char * __init prom_getcmdline(void) char * __init prom_getcmdline(void)
{ {
return &(arcs_cmdline[0]); return &(arcs_cmdline[0]);
...@@ -60,6 +50,8 @@ void __init prom_init_cmdline(void) ...@@ -60,6 +50,8 @@ void __init prom_init_cmdline(void)
{ {
char *cp; char *cp;
int actr; int actr;
int prom_argc = fw_arg0;
char **prom_argv = (char **) fw_arg1;
actr = 1; /* Always ignore argv[0] */ actr = 1; /* Always ignore argv[0] */
......
arch/mips/jmr3927/common/puts.c
View file @ 2127435e
...@@ -32,137 +32,29 @@ ...@@ -32,137 +32,29 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/types.h>
#include <asm/jmr3927/txx927.h>
#include <asm/jmr3927/tx3927.h> #include <asm/jmr3927/tx3927.h>
#include <asm/jmr3927/jmr3927.h>
#define TIMEOUT 0xffffff #define TIMEOUT 0xffffff
#define SLOW_DOWN
static const char digits[16] = "0123456789abcdef";
#ifdef SLOW_DOWN
#define slow_down() { int k; for (k=0; k<10000; k++); }
#else
#define slow_down()
#endif
void void
putch(const unsigned char c) prom_putchar(char c)
{ {
int i = 0; int i = 0;
do { do {
slow_down();
i++; i++;
if (i>TIMEOUT) { if (i>TIMEOUT)
break; break;
}
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(1)->tfifo = c; tx3927_sioptr(1)->tfifo = c;
return; return;
} }
unsigned char getch(void)
{
int i = 0;
int dicr;
char c;
/* diable RX int. */
dicr = tx3927_sioptr(1)->dicr;
tx3927_sioptr(1)->dicr = 0;
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID)
;
c = tx3927_sioptr(1)->rfifo;
/* clear RX int. status */
tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS;
/* enable RX int. */
tx3927_sioptr(1)->dicr = dicr;
return c;
}
void
do_jmr3927_led_set(char n)
{
/* and with current leds */
jmr3927_led_and_set(n);
}
void void
puts(unsigned char *cp) puts(const char *cp)
{ {
int i = 0; while (*cp)
prom_putchar(*cp++);
while (*cp) { prom_putchar('\r');
do { prom_putchar('\n');
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(1)->tfifo = *cp++;
}
putch('\r');
putch('\n');
}
void
fputs(unsigned char *cp)
{
int i = 0;
while (*cp) {
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(1)->tfifo = *cp++;
}
}
void
put64(uint64_t ul)
{
int cnt;
unsigned ch;
cnt = 16; /* 16 nibbles in a 64 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
void
put32(unsigned u)
{
int cnt;
unsigned ch;
cnt = 8; /* 8 nibbles in a 32 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char)(u >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
} }
arch/mips/jmr3927/rbhma3100/Makefile
View file @ 2127435e
...@@ -3,5 +3,4 @@ ...@@ -3,5 +3,4 @@
# #
obj-y += init.o irq.o setup.o obj-y += init.o irq.o setup.o
obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
obj-$(CONFIG_KGDB) += kgdb_io.o obj-$(CONFIG_KGDB) += kgdb_io.o
arch/mips/jmr3927/rbhma3100/init.c
View file @ 2127435e
...@@ -28,20 +28,10 @@ ...@@ -28,20 +28,10 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/jmr3927/jmr3927.h> #include <asm/jmr3927/jmr3927.h>
int prom_argc;
char **prom_argv, **prom_envp;
extern void __init prom_init_cmdline(void); extern void __init prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
unsigned long mips_nofpu = 0;
const char *get_system_type(void) const char *get_system_type(void)
{ {
...@@ -52,7 +42,7 @@ const char *get_system_type(void) ...@@ -52,7 +42,7 @@ const char *get_system_type(void)
; ;
} }
extern void puts(unsigned char *cp); extern void puts(const char *cp);
void __init prom_init(void) void __init prom_init(void)
{ {
...@@ -61,10 +51,6 @@ void __init prom_init(void) ...@@ -61,10 +51,6 @@ void __init prom_init(void)
if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
puts("Warning: TX3927 TLB off\n"); puts("Warning: TX3927 TLB off\n");
#endif #endif
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_TOSHIBA; mips_machgroup = MACH_GROUP_TOSHIBA;
#ifdef CONFIG_TOSHIBA_JMR3927 #ifdef CONFIG_TOSHIBA_JMR3927
......
arch/mips/jmr3927/rbhma3100/irq.c
View file @ 2127435e
This diff is collapsed.
arch/mips/jmr3927/rbhma3100/kgdb_io.c
View file @ 2127435e
...@@ -31,23 +31,12 @@ ...@@ -31,23 +31,12 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/types.h>
#include <asm/jmr3927/txx927.h>
#include <asm/jmr3927/tx3927.h>
#include <asm/jmr3927/jmr3927.h> #include <asm/jmr3927/jmr3927.h>
#define TIMEOUT 0xffffff #define TIMEOUT 0xffffff
#define SLOW_DOWN
static const char digits[16] = "0123456789abcdef";
#ifdef SLOW_DOWN
#define slow_down() { int k; for (k=0; k<10000; k++); }
#else
#define slow_down()
#endif
static int remoteDebugInitialized = 0; static int remoteDebugInitialized = 0;
static void debugInit(int baud)
int putDebugChar(unsigned char c) int putDebugChar(unsigned char c)
{ {
...@@ -103,20 +92,8 @@ unsigned char getDebugChar(void) ...@@ -103,20 +92,8 @@ unsigned char getDebugChar(void)
return c; return c;
} }
void debugInit(int baud) static void debugInit(int baud)
{ {
/*
volatile unsigned long lcr;
volatile unsigned long dicr;
volatile unsigned long disr;
volatile unsigned long cisr;
volatile unsigned long fcr;
volatile unsigned long flcr;
volatile unsigned long bgr;
volatile unsigned long tfifo;
volatile unsigned long rfifo;
*/
tx3927_sioptr(0)->lcr = 0x020; tx3927_sioptr(0)->lcr = 0x020;
tx3927_sioptr(0)->dicr = 0; tx3927_sioptr(0)->dicr = 0;
tx3927_sioptr(0)->disr = 0x4100; tx3927_sioptr(0)->disr = 0x4100;
...@@ -125,31 +102,4 @@ void debugInit(int baud) ...@@ -125,31 +102,4 @@ void debugInit(int baud)
tx3927_sioptr(0)->flcr = 0x02; tx3927_sioptr(0)->flcr = 0x02;
tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
TXx927_SIBGR_BCLK_T0; TXx927_SIBGR_BCLK_T0;
#if 0
/*
* Reset the UART.
*/
tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
;
/*
* and set the speed of the serial port
* (currently hardwired to 9600 8N1
*/
tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
TXx927_SILCR_USBL_1BIT |
TXx927_SILCR_SCS_IMCLK_BG;
tx3927_sioptr(0)->bgr =
((JMR3927_BASE_BAUD + baud / 2) / baud) |
TXx927_SIBGR_BCLK_T0;
/* HW RTS/CTS control */
if (ser->flags & ASYNC_HAVE_CTS_LINE)
tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
TXx927_SIFLCR_RTSTL_MAX /* 15 */;
/* Enable RX/TX */
tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
#endif
} }
arch/mips/jmr3927/rbhma3100/setup.c
View file @ 2127435e
...@@ -54,87 +54,18 @@ ...@@ -54,87 +54,18 @@
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/jmr3927/jmr3927.h> #include <asm/jmr3927/jmr3927.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/traps.h>
extern void puts(unsigned char *cp); extern void puts(const char *cp);
/* Tick Timer divider */ /* Tick Timer divider */
#define JMR3927_TIMER_CCD 0 /* 1/2 */ #define JMR3927_TIMER_CCD 0 /* 1/2 */
#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD)) #define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
unsigned char led_state = 0xf;
struct {
struct resource ram0;
struct resource ram1;
struct resource pcimem;
struct resource iob;
struct resource ioc;
struct resource pciio;
struct resource jmy1394;
struct resource rom1;
struct resource rom0;
struct resource sio0;
struct resource sio1;
} jmr3927_resources = {
{
.start = 0,
.end = 0x01FFFFFF,
.name = "RAM0",
.flags = IORESOURCE_MEM
}, {
.start = 0x02000000,
.end = 0x03FFFFFF,
.name = "RAM1",
.flags = IORESOURCE_MEM
}, {
.start = 0x08000000,
.end = 0x07FFFFFF,
.name = "PCIMEM",
.flags = IORESOURCE_MEM
}, {
.start = 0x10000000,
.end = 0x13FFFFFF,
.name = "IOB"
}, {
.start = 0x14000000,
.end = 0x14FFFFFF,
.name = "IOC"
}, {
.start = 0x15000000,
.end = 0x15FFFFFF,
.name = "PCIIO"
}, {
.start = 0x1D000000,
.end = 0x1D3FFFFF,
.name = "JMY1394"
}, {
.start = 0x1E000000,
.end = 0x1E3FFFFF,
.name = "ROM1"
}, {
.start = 0x1FC00000,
.end = 0x1FFFFFFF,
.name = "ROM0"
}, {
.start = 0xFFFEF300,
.end = 0xFFFEF3FF,
.name = "SIO0"
}, {
.start = 0xFFFEF400,
.end = 0xFFFEF4FF,
.name = "SIO1"
},
};
/* don't enable - see errata */ /* don't enable - see errata */
int jmr3927_ccfg_toeon = 0; static int jmr3927_ccfg_toeon;
static inline void do_reset(void) static inline void do_reset(void)
{ {
...@@ -173,9 +104,15 @@ static cycle_t jmr3927_hpt_read(void) ...@@ -173,9 +104,15 @@ static cycle_t jmr3927_hpt_read(void)
return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
} }
static void jmr3927_timer_ack(void)
{
jmr3927_tmrptr->tisr = 0; /* ack interrupt */
}
static void __init jmr3927_time_init(void) static void __init jmr3927_time_init(void)
{ {
clocksource_mips.read = jmr3927_hpt_read; clocksource_mips.read = jmr3927_hpt_read;
mips_timer_ack = jmr3927_timer_ack;
mips_hpt_frequency = JMR3927_TIMER_CLK; mips_hpt_frequency = JMR3927_TIMER_CLK;
} }
...@@ -190,9 +127,6 @@ void __init plat_timer_setup(struct irqaction *irq) ...@@ -190,9 +127,6 @@ void __init plat_timer_setup(struct irqaction *irq)
setup_irq(JMR3927_IRQ_TICK, irq); setup_irq(JMR3927_IRQ_TICK, irq);
} }
#define USECS_PER_JIFFY (1000000/HZ)
//#undef DO_WRITE_THROUGH
#define DO_WRITE_THROUGH #define DO_WRITE_THROUGH
#define DO_ENABLE_CACHE #define DO_ENABLE_CACHE
...@@ -224,12 +158,6 @@ void __init plat_mem_setup(void) ...@@ -224,12 +158,6 @@ void __init plat_mem_setup(void)
/* Reboot on panic */ /* Reboot on panic */
panic_timeout = 180; panic_timeout = 180;
{
unsigned int conf;
conf = read_c0_conf();
}
#if 1
/* cache setup */ /* cache setup */
{ {
unsigned int conf; unsigned int conf;
...@@ -256,16 +184,14 @@ void __init plat_mem_setup(void) ...@@ -256,16 +184,14 @@ void __init plat_mem_setup(void)
write_c0_conf(conf); write_c0_conf(conf);
write_c0_cache(0); write_c0_cache(0);
} }
#endif
/* initialize board */ /* initialize board */
jmr3927_board_init(); jmr3927_board_init();
argptr = prom_getcmdline(); argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "toeon")) != NULL) { if ((argptr = strstr(argptr, "toeon")) != NULL)
jmr3927_ccfg_toeon = 1; jmr3927_ccfg_toeon = 1;
}
argptr = prom_getcmdline(); argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "ip=")) == NULL) { if ((argptr = strstr(argptr, "ip=")) == NULL) {
argptr = prom_getcmdline(); argptr = prom_getcmdline();
...@@ -281,7 +207,7 @@ void __init plat_mem_setup(void) ...@@ -281,7 +207,7 @@ void __init plat_mem_setup(void)
memset(&req, 0, sizeof(req)); memset(&req, 0, sizeof(req));
req.line = i; req.line = i;
req.iotype = UPIO_MEM; req.iotype = UPIO_MEM;
req.membase = (char *)TX3927_SIO_REG(i); req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
req.mapbase = TX3927_SIO_REG(i); req.mapbase = TX3927_SIO_REG(i);
req.irq = i == 0 ? req.irq = i == 0 ?
JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
...@@ -303,65 +229,33 @@ void __init plat_mem_setup(void) ...@@ -303,65 +229,33 @@ void __init plat_mem_setup(void)
static void tx3927_setup(void); static void tx3927_setup(void);
#ifdef CONFIG_PCI
unsigned long mips_pci_io_base;
unsigned long mips_pci_io_size;
unsigned long mips_pci_mem_base;
unsigned long mips_pci_mem_size;
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
unsigned long mips_pci_io_pciaddr = 0;
#endif
static void __init jmr3927_board_init(void) static void __init jmr3927_board_init(void)
{ {
char *argptr;
#ifdef CONFIG_PCI
mips_pci_io_base = JMR3927_PCIIO;
mips_pci_io_size = JMR3927_PCIIO_SIZE;
mips_pci_mem_base = JMR3927_PCIMEM;
mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
#endif
tx3927_setup(); tx3927_setup();
if (jmr3927_have_isac()) {
#ifdef CONFIG_FB_E1355
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "video=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " video=e1355fb:crt16h");
}
#endif
#ifdef CONFIG_BLK_DEV_IDE
/* overrides PCI-IDE */
#endif
}
/* SIO0 DTR on */ /* SIO0 DTR on */
jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
jmr3927_led_set(0); jmr3927_led_set(0);
if (jmr3927_have_isac())
jmr3927_io_led_set(0);
printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw1(), jmr3927_dipsw2(),
jmr3927_dipsw3(), jmr3927_dipsw4()); jmr3927_dipsw3(), jmr3927_dipsw4());
if (jmr3927_have_isac())
printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
jmr3927_io_dipsw());
} }
void __init tx3927_setup(void) static void __init tx3927_setup(void)
{ {
int i; int i;
#ifdef CONFIG_PCI
unsigned long mips_pci_io_base = JMR3927_PCIIO;
unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
unsigned long mips_pci_io_pciaddr = 0;
#endif
/* SDRAMC are configured by PROM */ /* SDRAMC are configured by PROM */
...@@ -475,10 +369,8 @@ void __init tx3927_setup(void) ...@@ -475,10 +369,8 @@ void __init tx3927_setup(void)
tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
tx3927_pcicptr->mba = 0; tx3927_pcicptr->mba = 0;
tx3927_pcicptr->tlbmma = 0; tx3927_pcicptr->tlbmma = 0;
#ifndef JMR3927_INIT_INDIRECT_PCI
/* Enable Direct mapping Address Space Decoder */ /* Enable Direct mapping Address Space Decoder */
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
#endif
/* Clear All Local Bus Status */ /* Clear All Local Bus Status */
tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
...@@ -491,22 +383,15 @@ void __init tx3927_setup(void) ...@@ -491,22 +383,15 @@ void __init tx3927_setup(void)
/* PCIC Int => IRC IRQ10 */ /* PCIC Int => IRC IRQ10 */
tx3927_pcicptr->il = TX3927_IR_PCI; tx3927_pcicptr->il = TX3927_IR_PCI;
#if 1
/* Target Control (per errata) */ /* Target Control (per errata) */
tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
#endif
/* Enable Bus Arbiter */ /* Enable Bus Arbiter */
#if 0
tx3927_pcicptr->req_trace = 0x73737373;
#endif
tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_MEMORY |
#if 1
PCI_COMMAND_IO | PCI_COMMAND_IO |
#endif
PCI_COMMAND_PARITY | PCI_COMMAND_SERR; PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
} }
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
...@@ -555,8 +440,6 @@ static int __init jmr3927_rtc_init(void) ...@@ -555,8 +440,6 @@ static int __init jmr3927_rtc_init(void)
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}; };
struct platform_device *dev; struct platform_device *dev;
if (!jmr3927_have_nvram())
return -ENODEV;
dev = platform_device_register_simple("ds1742", -1, &res, 1); dev = platform_device_register_simple("ds1742", -1, &res, 1);
return IS_ERR(dev) ? PTR_ERR(dev) : 0; return IS_ERR(dev) ? PTR_ERR(dev) : 0;
} }
......
arch/mips/pci/fixup-jmr3927.c
View file @ 2127435e
...@@ -29,7 +29,6 @@ ...@@ -29,7 +29,6 @@
*/ */
#include <linux/types.h> #include <linux/types.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/jmr3927/jmr3927.h> #include <asm/jmr3927/jmr3927.h>
...@@ -81,14 +80,8 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ...@@ -81,14 +80,8 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */ /* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
if (dev->bus->parent == NULL && if (dev->bus->parent == NULL &&
slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24)) { slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24))
extern int jmr3927_ether1_irq; irq = JMR3927_IRQ_ETHER0;
/* check this irq line was reserved for ether1 */
if (jmr3927_ether1_irq != JMR3927_IRQ_ETHER0)
irq = JMR3927_IRQ_ETHER0;
else
irq = 0; /* disable */
}
return irq; return irq;
} }
......
arch/mips/pci/ops-tx3927.c
View file @ 2127435e
...@@ -40,7 +40,6 @@ ...@@ -40,7 +40,6 @@
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/jmr3927/jmr3927.h> #include <asm/jmr3927/jmr3927.h>
#include <asm/debug.h>
static inline int mkaddr(unsigned char bus, unsigned char dev_fn, static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
unsigned char where) unsigned char where)
...@@ -130,234 +129,3 @@ struct pci_ops jmr3927_pci_ops = { ...@@ -130,234 +129,3 @@ struct pci_ops jmr3927_pci_ops = {
jmr3927_pci_read_config, jmr3927_pci_read_config,
jmr3927_pci_write_config, jmr3927_pci_write_config,
}; };
#ifndef JMR3927_INIT_INDIRECT_PCI
inline unsigned long tc_readl(volatile __u32 * addr)
{
return readl(addr);
}
inline void tc_writel(unsigned long data, volatile __u32 * addr)
{
writel(data, addr);
}
#else
unsigned long tc_readl(volatile __u32 * addr)
{
unsigned long val;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) CPHYSADDR(addr);
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
PCI_IPCIBE_IBE_LONG;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
val =
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
ipcidata);
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
return val;
}
void tc_writel(unsigned long data, volatile __u32 * addr)
{
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
cpu_to_le32(data);
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) CPHYSADDR(addr);
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
PCI_IPCIBE_IBE_LONG;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
unsigned char tx_ioinb(unsigned char *addr)
{
unsigned long val;
__u32 ioaddr;
int offset;
int byte;
ioaddr = (unsigned long) addr;
offset = ioaddr & 0x3;
byte = 0xf & ~(8 >> offset);
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) ioaddr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
val =
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
ipcidata);
val = val & 0xff;
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
return val;
}
void tx_iooutb(unsigned long data, unsigned char *addr)
{
__u32 ioaddr;
int offset;
int byte;
data = data | (data << 8) | (data << 16) | (data << 24);
ioaddr = (unsigned long) addr;
offset = ioaddr & 0x3;
byte = 0xf & ~(8 >> offset);
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) ioaddr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
unsigned short tx_ioinw(unsigned short *addr)
{
unsigned long val;
__u32 ioaddr;
int offset;
int byte;
ioaddr = (unsigned long) addr;
offset = ioaddr & 0x2;
byte = 3 << offset;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) ioaddr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
val =
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
ipcidata);
val = val & 0xffff;
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
return val;
}
void tx_iooutw(unsigned long data, unsigned short *addr)
{
__u32 ioaddr;
int offset;
int byte;
data = data | (data << 16);
ioaddr = (unsigned long) addr;
offset = ioaddr & 0x2;
byte = 3 << offset;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) ioaddr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
unsigned long tx_ioinl(unsigned int *addr)
{
unsigned long val;
__u32 ioaddr;
ioaddr = (unsigned long) addr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) ioaddr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
PCI_IPCIBE_IBE_LONG;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
val =
le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
ipcidata);
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
return val;
}
void tx_iooutl(unsigned long data, unsigned int *addr)
{
__u32 ioaddr;
ioaddr = (unsigned long) addr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
cpu_to_le32(data);
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
(unsigned long) ioaddr;
*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
PCI_IPCIBE_IBE_LONG;
while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
/* clear by setting */
tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}
void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count)
{
unsigned char *ptr = (unsigned char *) buffer;
while (count--) {
*ptr++ = tx_ioinb(addr);
}
}
void tx_insword(unsigned short *addr, void *buffer, unsigned int count)
{
unsigned short *ptr = (unsigned short *) buffer;
while (count--) {
*ptr++ = tx_ioinw(addr);
}
}
void tx_inslong(unsigned int *addr, void *buffer, unsigned int count)
{
unsigned long *ptr = (unsigned long *) buffer;
while (count--) {
*ptr++ = tx_ioinl(addr);
}
}
void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count)
{
unsigned char *ptr = (unsigned char *) buffer;
while (count--) {
tx_iooutb(*ptr++, addr);
}
}
void tx_outsword(unsigned short *addr, void *buffer, unsigned int count)
{
unsigned short *ptr = (unsigned short *) buffer;
while (count--) {
tx_iooutw(*ptr++, addr);
}
}
void tx_outslong(unsigned int *addr, void *buffer, unsigned int count)
{
unsigned long *ptr = (unsigned long *) buffer;
while (count--) {
tx_iooutl(*ptr++, addr);
}
}
#endif
include/asm-mips/jmr3927/irq.h deleted 100644 → 0
View file @ 252161ec
/*
* linux/include/asm-mips/tx3927/irq.h
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Toshiba Corporation
*/
#ifndef __ASM_TX3927_IRQ_H
#define __ASM_TX3927_IRQ_H
#ifndef __ASSEMBLY__
#include <asm/irq.h>
struct tb_irq_space {
struct tb_irq_space* next;
int start_irqno;
int nr_irqs;
void (*mask_func)(int irq_nr, int space_id);
void (*unmask_func)(int irq_no, int space_id);
const char *name;
int space_id;
int can_share;
};
extern struct tb_irq_space* tb_irq_spaces;
static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
{
sp->next = tb_irq_spaces;
tb_irq_spaces = sp;
}
struct pt_regs;
extern void
toshibaboards_spurious(struct pt_regs *regs, int irq);
extern void
toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
extern struct irqaction *
toshibaboards_get_irq_action(int irq);
extern int
toshibaboards_setup_irq(int irq, struct irqaction * new);
extern int (*toshibaboards_gen_iack)(void);
#endif /* !__ASSEMBLY__ */
#define NR_ISA_IRQS 16
#define TB_IRQ_IS_ISA(irq) \
(0 <= (irq) && (irq) < NR_ISA_IRQS)
#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
#endif /* __ASM_TX3927_IRQ_H */
include/asm-mips/jmr3927/jmr3927.h
View file @ 2127435e
/* /*
* Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF. * Defines for the TJSYS JMR-TX3927
* *
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
...@@ -12,10 +12,7 @@ ...@@ -12,10 +12,7 @@
#include <asm/jmr3927/tx3927.h> #include <asm/jmr3927/tx3927.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/jmr3927/irq.h>
#ifndef __ASSEMBLY__
#include <asm/system.h> #include <asm/system.h>
#endif
/* CS */ /* CS */
#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ #define JMR3927_ROMCE0 0x1fc00000 /* 4M */
...@@ -35,28 +32,10 @@ ...@@ -35,28 +32,10 @@
#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ #define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
#define JMR3927_PORT_BASE KSEG1 #define JMR3927_PORT_BASE KSEG1
/* select indirect initiator access per errata */
#define JMR3927_INIT_INDIRECT_PCI
#define PCI_ISTAT_IDICC 0x1000
#define PCI_IPCIBE_IBE_LONG 0
#define PCI_IPCIBE_ICMD_IOREAD 2
#define PCI_IPCIBE_ICMD_IOWRITE 3
#define PCI_IPCIBE_ICMD_MEMREAD 6
#define PCI_IPCIBE_ICMD_MEMWRITE 7
#define PCI_IPCIBE_ICMD_SHIFT 4
/* Address map (virtual address) */ /* Address map (virtual address) */
#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) #define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) #define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) #define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) #define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) #define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
...@@ -72,25 +51,14 @@ ...@@ -72,25 +51,14 @@
#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) #define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) #define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
/* Flash ROM */ /* Flash ROM */
#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) #define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
#define JMR3927_FLASH_SIZE 0x00400000 #define JMR3927_FLASH_SIZE 0x00400000
/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */ /* bits for IOC_REV/IOC_BREV (high byte) */
#define JMR3927_IDT_MASK 0xfc #define JMR3927_IDT_MASK 0xfc
#define JMR3927_REV_MASK 0x03 #define JMR3927_REV_MASK 0x03
#define JMR3927_IOC_IDT 0xe0 #define JMR3927_IOC_IDT 0xe0
#define JMR3927_ISAC_IDT 0x20
/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ /* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
#define JMR3927_IOC_INTB_PCIA 0 #define JMR3927_IOC_INTB_PCIA 0
...@@ -114,40 +82,6 @@ ...@@ -114,40 +82,6 @@
#define JMR3927_IOC_RESET_CPU 1 #define JMR3927_IOC_RESET_CPU 1
#define JMR3927_IOC_RESET_PCI 2 #define JMR3927_IOC_RESET_PCI 2
/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
#define JMR3927_ISAC_EINTB_IOCHK 2
#define JMR3927_ISAC_EINTB_BWTH 4
#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
/* bits for ISAC_LED (high byte) */
#define JMR3927_ISAC_LED_ISALED 0x01
#define JMR3927_ISAC_LED_USRLED 0x02
/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
#define JMR3927_ISAC_INTB_IRQ5 0
#define JMR3927_ISAC_INTB_IRQKB 1
#define JMR3927_ISAC_INTB_IRQMOUSE 2
#define JMR3927_ISAC_INTB_IRQ4 3
#define JMR3927_ISAC_INTB_IRQ12 4
#define JMR3927_ISAC_INTB_IRQ3 5
#define JMR3927_ISAC_INTB_IRQ10 6
#define JMR3927_ISAC_INTB_ISAER 7
#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
#ifndef __ASSEMBLY__
#if 0
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
#else
#if defined(__BIG_ENDIAN) #if defined(__BIG_ENDIAN)
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) #define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) #define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
...@@ -157,31 +91,9 @@ ...@@ -157,31 +91,9 @@
#else #else
#error "No Endian" #error "No Endian"
#endif #endif
#endif
#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
static inline int jmr3927_have_isac(void)
{
unsigned char idt;
unsigned long flags;
unsigned long romcr3;
local_irq_save(flags);
romcr3 = tx3927_romcptr->cr[3];
tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
tx3927_romcptr->cr[3] = romcr3;
local_irq_restore(flags);
return idt == JMR3927_ISAC_IDT;
}
#define jmr3927_have_nvram() \
((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
/* LED macro */ /* LED macro */
#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) #define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) #define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
...@@ -190,10 +102,6 @@ static inline int jmr3927_have_isac(void) ...@@ -190,10 +102,6 @@ static inline int jmr3927_have_isac(void)
#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0) #define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) #define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) #define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
#endif /* !__ASSEMBLY__ */
/* /*
* IRQ mappings * IRQ mappings
...@@ -206,16 +114,10 @@ static inline int jmr3927_have_isac(void) ...@@ -206,16 +114,10 @@ static inline int jmr3927_have_isac(void)
*/ */
#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ #define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ #define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
#define JMR3927_IRQ_IRC 16
#define JMR3927_IRQ_IRC NR_ISA_IRQS
#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) #define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) #define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) #define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) #define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
...@@ -240,37 +142,13 @@ static inline int jmr3927_have_isac(void) ...@@ -240,37 +142,13 @@ static inline int jmr3927_have_isac(void)
#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) #define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) #define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) #define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
#if 0 /* auto detect */
/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
#endif
/* IOC (PCI, MODEM) */ /* IOC (PCI, MODEM) */
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 #define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ /* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 #define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
/* Clock Tick (10ms) */ /* Clock Tick (10ms) */
#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0 #define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
/* I/O Ports */
/* RTL8019AS 10M Ether */
#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
/* Clocks */ /* Clocks */
#define JMR3927_CORECLK 132710400 /* 132.7MHz */ #define JMR3927_CORECLK 132710400 /* 132.7MHz */
......
include/asm-mips/jmr3927/tx3927.h
View file @ 2127435e
...@@ -22,8 +22,6 @@ ...@@ -22,8 +22,6 @@
#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) #define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
#define TX3927_PIO_REG 0xfffef500 #define TX3927_PIO_REG 0xfffef500
#ifndef __ASSEMBLY__
struct tx3927_sdramc_reg { struct tx3927_sdramc_reg {
volatile unsigned long cr[8]; volatile unsigned long cr[8];
volatile unsigned long tr[3]; volatile unsigned long tr[3];
...@@ -164,8 +162,6 @@ struct tx3927_ccfg_reg { ...@@ -164,8 +162,6 @@ struct tx3927_ccfg_reg {
volatile unsigned long pdcr; volatile unsigned long pdcr;
}; };
#endif /* !__ASSEMBLY__ */
/* /*
* SDRAMC * SDRAMC
*/ */
...@@ -348,8 +344,6 @@ struct tx3927_ccfg_reg { ...@@ -348,8 +344,6 @@ struct tx3927_ccfg_reg {
#define TX3927_PCFG_SELDMA_ALL 0x0000000f #define TX3927_PCFG_SELDMA_ALL 0x0000000f
#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) #define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
#ifndef __ASSEMBLY__
#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) #define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) #define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) #define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
...@@ -360,6 +354,4 @@ struct tx3927_ccfg_reg { ...@@ -360,6 +354,4 @@ struct tx3927_ccfg_reg {
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG) #define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_TX3927_H */ #endif /* __ASM_TX3927_H */
include/asm-mips/jmr3927/txx927.h
View file @ 2127435e
...@@ -10,8 +10,6 @@ ...@@ -10,8 +10,6 @@
#ifndef __ASM_TXX927_H #ifndef __ASM_TXX927_H
#define __ASM_TXX927_H #define __ASM_TXX927_H
#ifndef __ASSEMBLY__
struct txx927_tmr_reg { struct txx927_tmr_reg {
volatile unsigned long tcr; volatile unsigned long tcr;
volatile unsigned long tisr; volatile unsigned long tisr;
...@@ -52,9 +50,6 @@ struct txx927_pio_reg { ...@@ -52,9 +50,6 @@ struct txx927_pio_reg {
volatile unsigned long maskext; volatile unsigned long maskext;
}; };
#endif /* !__ASSEMBLY__ */
/* /*
* TMR * TMR
*/ */
......
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