Commit 23bfb5be authored by Andrew Miller's avatar Andrew Miller Committed by Mauro Carvalho Chehab

[media] Staging: media: solo6x10: core.c Fix some coding style issue

Replaced spaces with tabs
Signed-off-by: default avatarAndrew Miller <amiller@amilx.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 68a6bb54
......@@ -195,28 +195,28 @@ static int __devinit solo_pci_probe(struct pci_dev *pdev,
SOLO6010_SYS_CFG_OUTDIV(3);
solo_reg_write(solo_dev, SOLO_SYS_CFG, reg);
if (solo_dev->flags & FLAGS_6110) {
u32 sys_clock_MHz = SOLO_CLOCK_MHZ;
u32 pll_DIVQ;
u32 pll_DIVF;
if (sys_clock_MHz < 125) {
pll_DIVQ = 3;
pll_DIVF = (sys_clock_MHz * 4) / 3;
} else {
pll_DIVQ = 2;
pll_DIVF = (sys_clock_MHz * 2) / 3;
}
solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG,
if (solo_dev->flags & FLAGS_6110) {
u32 sys_clock_MHz = SOLO_CLOCK_MHZ;
u32 pll_DIVQ;
u32 pll_DIVF;
if (sys_clock_MHz < 125) {
pll_DIVQ = 3;
pll_DIVF = (sys_clock_MHz * 4) / 3;
} else {
pll_DIVQ = 2;
pll_DIVF = (sys_clock_MHz * 2) / 3;
}
solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG,
SOLO6110_PLL_RANGE_5_10MHZ |
SOLO6110_PLL_DIVR(9) |
SOLO6110_PLL_DIVQ_EXP(pll_DIVQ) |
SOLO6110_PLL_DIVF(pll_DIVF) | SOLO6110_PLL_FSEN);
mdelay(1); // PLL Locking time (1ms)
mdelay(1); /* PLL Locking time (1ms) */
solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 3 << 8); /* ? */
} else
} else
solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 1 << 8); /* ? */
solo_reg_write(solo_dev, SOLO_TIMER_CLOCK_NUM, SOLO_CLOCK_MHZ - 1);
......
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