Commit 242613af authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson

drm/i915: Use the gt in HAS_ENGINE

A follow up patch will move the engine mask under the gt structure,
so get ready for that.

v2: switch the remaining gvt case using dev_priv->gt to gvt->gt (Chris)
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> #v1
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-3-daniele.ceraolospurio@intel.com
parent fdeb6d02
...@@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) ...@@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt)
return -ENODEV; return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
if (!HAS_ENGINE(i915, i)) if (!HAS_ENGINE(gt, i))
continue; continue;
err = intel_engine_setup(gt, i); err = intel_engine_setup(gt, i);
......
...@@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt) ...@@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
* RPS interrupts will get enabled/disabled on demand when RPS * RPS interrupts will get enabled/disabled on demand when RPS
* itself is enabled/disabled. * itself is enabled/disabled.
*/ */
if (HAS_ENGINE(gt->i915, VECS0)) { if (HAS_ENGINE(gt, VECS0)) {
pm_irqs |= PM_VEBOX_USER_INTERRUPT; pm_irqs |= PM_VEBOX_USER_INTERRUPT;
gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;
} }
......
...@@ -67,7 +67,8 @@ struct __guc_ads_blob { ...@@ -67,7 +67,8 @@ struct __guc_ads_blob {
static void __guc_ads_init(struct intel_guc *guc) static void __guc_ads_init(struct intel_guc *guc)
{ {
struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *dev_priv = gt->i915;
struct __guc_ads_blob *blob = guc->ads_blob; struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base; u32 base;
...@@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc) ...@@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->system_info.rcs_enabled = 1; blob->system_info.rcs_enabled = 1;
blob->system_info.bcs_enabled = 1; blob->system_info.bcs_enabled = 1;
blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv); blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);
blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv); blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);
blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
base = intel_guc_ggtt_offset(guc, guc->ads_vma); base = intel_guc_ggtt_offset(guc, guc->ads_vma);
......
...@@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, ...@@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
if (HAS_ENGINE(dev_priv, VCS1)) \ if (HAS_ENGINE(gvt->gt, VCS1)) \
MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
} while (0) } while (0)
......
...@@ -540,7 +540,7 @@ static void gen8_init_irq( ...@@ -540,7 +540,7 @@ static void gen8_init_irq(
SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
if (HAS_ENGINE(gvt->gt->i915, VCS1)) { if (HAS_ENGINE(gvt->gt, VCS1)) {
SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
INTEL_GVT_IRQ_INFO_GT1); INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
......
...@@ -171,7 +171,7 @@ static void load_render_mocs(const struct intel_engine_cs *engine) ...@@ -171,7 +171,7 @@ static void load_render_mocs(const struct intel_engine_cs *engine)
return; return;
for (ring_id = 0; ring_id < cnt; ring_id++) { for (ring_id = 0; ring_id < cnt; ring_id++) {
if (!HAS_ENGINE(engine->i915, ring_id)) if (!HAS_ENGINE(engine->gt, ring_id))
continue; continue;
offset.reg = regs[ring_id]; offset.reg = regs[ring_id];
......
...@@ -533,7 +533,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) ...@@ -533,7 +533,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
intel_device_info_init_mmio(dev_priv); intel_device_info_init_mmio(dev_priv);
intel_uncore_prune_mmio_domains(&dev_priv->uncore); intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt);
intel_uc_init_mmio(&dev_priv->gt.uc); intel_uc_init_mmio(&dev_priv->gt.uc);
......
...@@ -1562,18 +1562,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, ...@@ -1562,18 +1562,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id)
#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
unsigned int first__ = (first); \ unsigned int first__ = (first); \
unsigned int count__ = (count); \ unsigned int count__ = (count); \
(INTEL_INFO(dev_priv)->engine_mask & \ (INTEL_INFO((gt)->i915)->engine_mask & \
GENMASK(first__ + count__ - 1, first__)) >> first__; \ GENMASK(first__ + count__ - 1, first__)) >> first__; \
}) })
#define VDBOX_MASK(dev_priv) \ #define VDBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(dev_priv) \ #define VEBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
/* /*
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
......
...@@ -1100,6 +1100,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) ...@@ -1100,6 +1100,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
{ {
struct intel_device_info *info = mkwrite_device_info(dev_priv); struct intel_device_info *info = mkwrite_device_info(dev_priv);
struct intel_uncore *uncore = &dev_priv->uncore; struct intel_uncore *uncore = &dev_priv->uncore;
struct intel_gt *gt = &dev_priv->gt;
unsigned int logical_vdbox = 0; unsigned int logical_vdbox = 0;
unsigned int i; unsigned int i;
u32 media_fuse; u32 media_fuse;
...@@ -1116,7 +1117,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) ...@@ -1116,7 +1117,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
GEN11_GT_VEBOX_DISABLE_SHIFT; GEN11_GT_VEBOX_DISABLE_SHIFT;
for (i = 0; i < I915_MAX_VCS; i++) { for (i = 0; i < I915_MAX_VCS; i++) {
if (!HAS_ENGINE(dev_priv, _VCS(i))) { if (!HAS_ENGINE(gt, _VCS(i))) {
vdbox_mask &= ~BIT(i); vdbox_mask &= ~BIT(i);
continue; continue;
} }
...@@ -1136,11 +1137,11 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) ...@@ -1136,11 +1137,11 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
} }
drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n",
vdbox_mask, VDBOX_MASK(dev_priv)); vdbox_mask, VDBOX_MASK(gt));
GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
for (i = 0; i < I915_MAX_VECS; i++) { for (i = 0; i < I915_MAX_VECS; i++) {
if (!HAS_ENGINE(dev_priv, _VECS(i))) { if (!HAS_ENGINE(gt, _VECS(i))) {
vebox_mask &= ~BIT(i); vebox_mask &= ~BIT(i);
continue; continue;
} }
...@@ -1151,6 +1152,6 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) ...@@ -1151,6 +1152,6 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
} }
} }
drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n",
vebox_mask, VEBOX_MASK(dev_priv)); vebox_mask, VEBOX_MASK(gt));
GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
} }
...@@ -7114,7 +7114,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) ...@@ -7114,7 +7114,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
/* This is not a WA. Enable VD HCP & MFX_ENC powergate */ /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
for (i = 0; i < I915_MAX_VCS; i++) { for (i = 0; i < I915_MAX_VCS; i++) {
if (HAS_ENGINE(dev_priv, _VCS(i))) if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) | vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
VDN_MFX_POWERGATE_ENABLE(i); VDN_MFX_POWERGATE_ENABLE(i);
} }
......
...@@ -1529,6 +1529,8 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) ...@@ -1529,6 +1529,8 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
(ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
if (INTEL_GEN(i915) >= 11) { if (INTEL_GEN(i915) >= 11) {
/* we'll prune the domains of missing engines later */
intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask;
int i; int i;
uncore->funcs.force_wake_get = fw_domains_get_with_fallback; uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
...@@ -1541,7 +1543,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) ...@@ -1541,7 +1543,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE_ACK_BLITTER_GEN9); FORCEWAKE_ACK_BLITTER_GEN9);
for (i = 0; i < I915_MAX_VCS; i++) { for (i = 0; i < I915_MAX_VCS; i++) {
if (!HAS_ENGINE(i915, _VCS(i))) if (!__HAS_ENGINE(emask, _VCS(i)))
continue; continue;
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
...@@ -1549,7 +1551,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) ...@@ -1549,7 +1551,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
} }
for (i = 0; i < I915_MAX_VECS; i++) { for (i = 0; i < I915_MAX_VECS; i++) {
if (!HAS_ENGINE(i915, _VECS(i))) if (!__HAS_ENGINE(emask, _VECS(i)))
continue; continue;
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
...@@ -1844,20 +1846,20 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) ...@@ -1844,20 +1846,20 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
* the forcewake domains. Prune them, to make sure they only reference existing * the forcewake domains. Prune them, to make sure they only reference existing
* engines. * engines.
*/ */
void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt)
{ {
struct drm_i915_private *i915 = uncore->i915;
enum forcewake_domains fw_domains = uncore->fw_domains; enum forcewake_domains fw_domains = uncore->fw_domains;
enum forcewake_domain_id domain_id; enum forcewake_domain_id domain_id;
int i; int i;
if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11) if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11)
return; return;
for (i = 0; i < I915_MAX_VCS; i++) { for (i = 0; i < I915_MAX_VCS; i++) {
domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
if (HAS_ENGINE(i915, _VCS(i))) if (HAS_ENGINE(gt, _VCS(i)))
continue; continue;
if (fw_domains & BIT(domain_id)) if (fw_domains & BIT(domain_id))
...@@ -1867,7 +1869,7 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) ...@@ -1867,7 +1869,7 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
for (i = 0; i < I915_MAX_VECS; i++) { for (i = 0; i < I915_MAX_VECS; i++) {
domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
if (HAS_ENGINE(i915, _VECS(i))) if (HAS_ENGINE(gt, _VECS(i)))
continue; continue;
if (fw_domains & BIT(domain_id)) if (fw_domains & BIT(domain_id))
......
...@@ -35,6 +35,7 @@ ...@@ -35,6 +35,7 @@
struct drm_i915_private; struct drm_i915_private;
struct intel_runtime_pm; struct intel_runtime_pm;
struct intel_uncore; struct intel_uncore;
struct intel_gt;
struct intel_uncore_mmio_debug { struct intel_uncore_mmio_debug {
spinlock_t lock; /** lock is also taken in irq contexts. */ spinlock_t lock; /** lock is also taken in irq contexts. */
...@@ -186,7 +187,8 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); ...@@ -186,7 +187,8 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore, void intel_uncore_init_early(struct intel_uncore *uncore,
struct drm_i915_private *i915); struct drm_i915_private *i915);
int intel_uncore_init_mmio(struct intel_uncore *uncore); int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore); void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt);
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
void intel_uncore_fini_mmio(struct intel_uncore *uncore); void intel_uncore_fini_mmio(struct intel_uncore *uncore);
......
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