Commit 24a8d289 authored by Christian König's avatar Christian König Committed by Alex Deucher

drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper v2

Helper to get the PDE for a PD/PT.

v2: improve documentation
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarJunwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bbc9fb10
...@@ -26,6 +26,38 @@ ...@@ -26,6 +26,38 @@
#include "amdgpu.h" #include "amdgpu.h"
/**
* amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
*
* @bo: the BO to get the PDE for
* @level: the level in the PD hirarchy
* @addr: resulting addr
* @flags: resulting flags
*
* Get the address and flags to be used for a PDE (Page Directory Entry).
*/
void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
uint64_t *addr, uint64_t *flags)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct ttm_dma_tt *ttm;
switch (bo->tbo.mem.mem_type) {
case TTM_PL_TT:
ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
*addr = ttm->dma_address[0];
break;
case TTM_PL_VRAM:
*addr = amdgpu_bo_gpu_offset(bo);
break;
default:
*addr = 0;
break;
}
*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
}
/** /**
* amdgpu_gmc_pd_addr - return the address of the root directory * amdgpu_gmc_pd_addr - return the address of the root directory
* *
...@@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) ...@@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
uint64_t pd_addr; uint64_t pd_addr;
pd_addr = amdgpu_bo_gpu_offset(bo);
/* TODO: move that into ASIC specific code */ /* TODO: move that into ASIC specific code */
if (adev->asic_type >= CHIP_VEGA10) { if (adev->asic_type >= CHIP_VEGA10) {
uint64_t flags = AMDGPU_PTE_VALID; uint64_t flags = AMDGPU_PTE_VALID;
amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags); amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
pd_addr |= flags; pd_addr |= flags;
} else {
pd_addr = amdgpu_bo_gpu_offset(bo);
} }
return pd_addr; return pd_addr;
} }
...@@ -133,6 +133,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) ...@@ -133,6 +133,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
return (gmc->real_vram_size == gmc->visible_vram_size); return (gmc->real_vram_size == gmc->visible_vram_size);
} }
void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
uint64_t *addr, uint64_t *flags);
uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
#endif #endif
...@@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) ...@@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
} }
/** /**
* amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
* *
* @ttm: The ttm_tt object to compute the flags for * @ttm: The ttm_tt object to compute the flags for
* @mem: The memory registry backing this ttm_tt object * @mem: The memory registry backing this ttm_tt object
*
* Figure out the flags to use for a VM PDE (Page Directory Entry).
*/ */
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
struct ttm_mem_reg *mem)
{ {
uint64_t flags = 0; uint64_t flags = 0;
...@@ -1448,6 +1449,22 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, ...@@ -1448,6 +1449,22 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
flags |= AMDGPU_PTE_SNOOPED; flags |= AMDGPU_PTE_SNOOPED;
} }
return flags;
}
/**
* amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
*
* @ttm: The ttm_tt object to compute the flags for
* @mem: The memory registry backing this ttm_tt object
* Figure out the flags to use for a VM PTE (Page Table Entry).
*/
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem)
{
uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
flags |= adev->gart.gart_pte_flags; flags |= adev->gart.gart_pte_flags;
flags |= AMDGPU_PTE_READABLE; flags |= AMDGPU_PTE_READABLE;
......
...@@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, ...@@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
int *last_invalidated); int *last_invalidated);
bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm); bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
struct ttm_mem_reg *mem); struct ttm_mem_reg *mem);
......
...@@ -1014,9 +1014,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, ...@@ -1014,9 +1014,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
pbo = pbo->parent; pbo = pbo->parent;
level += params->adev->vm_manager.root_level; level += params->adev->vm_manager.root_level;
pt = amdgpu_bo_gpu_offset(entry->base.bo); amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
flags = AMDGPU_PTE_VALID;
amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
pde = (entry - parent->entries) * 8; pde = (entry - parent->entries) * 8;
if (bo->shadow) if (bo->shadow)
params->func(params, bo->shadow, pde, pt, 1, 0, flags); params->func(params, bo->shadow, pde, pt, 1, 0, flags);
......
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