Commit 24d504a3 authored by Tero Kristo's avatar Tero Kristo

clk: ti: dra7: add clkctrl clock data

Add data for dra7 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent ae263d52
This diff is collapsed.
...@@ -452,6 +452,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) ...@@ -452,6 +452,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if (of_machine_is_compatible("ti,omap5")) if (of_machine_is_compatible("ti,omap5"))
data = omap5_clkctrl_data; data = omap5_clkctrl_data;
#endif #endif
#ifdef CONFIG_SOC_DRA7XX
if (of_machine_is_compatible("ti,dra7"))
data = dra7_clkctrl_data;
#endif
while (data->addr) { while (data->addr) {
if (addr == data->addr) if (addr == data->addr)
......
...@@ -232,6 +232,7 @@ struct omap_clkctrl_data { ...@@ -232,6 +232,7 @@ struct omap_clkctrl_data {
extern const struct omap_clkctrl_data omap4_clkctrl_data[]; extern const struct omap_clkctrl_data omap4_clkctrl_data[];
extern const struct omap_clkctrl_data omap5_clkctrl_data[]; extern const struct omap_clkctrl_data omap5_clkctrl_data[];
extern const struct omap_clkctrl_data dra7_clkctrl_data[];
#define CLKF_SW_SUP BIT(0) #define CLKF_SW_SUP BIT(0)
#define CLKF_HW_SUP BIT(1) #define CLKF_HW_SUP BIT(1)
......
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