[PATCH] ppc32: PPC4xx fixes

From: Matt Porter <mporter@kernel.crashing.org>

Fixes 440GX UIC code, updates 440GX PVRs, and fixes a typo.

arch/ppc/kernel/cputable.c

@@ -545,8 +545,8 @@ struct cpu_spec	cpu_specs[] = {
         32, 32,
         0, /*__setup_cpu_440 */
     },
-    { /* 440GX Rev. B1 (2.1) */
-        0xf0000fff, 0x50000852, "440GX Rev. B1 (2.1)",
+    { /* 440GX Rev. C */
+        0xf0000fff, 0x50000892, "440GX Rev. C",
         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
         32, 32,

arch/ppc/platforms/4xx/ibm440gp.c

@@ -125,7 +125,7 @@ struct ocp_def core_ocp[] = {
 	{ .vendor	= OCP_VENDOR_IBM,
 	  .function	= OCP_FUNC_EMAC,
 	  .index	= 0,
-	  .paddr	= 0x0000000140000800UL,
+	  .paddr	= 0x0000000140000800ULL,
 	  .irq		= 60,
 	  .pm		= OCP_CPM_NA,
 	  .additions	= &ibm440gp_emac0_def,

arch/ppc/syslib/ppc4xx_pic.c

@@ -173,14 +173,14 @@ ppc4xx_uic_enable(unsigned int irq)
 			desc->status |= IRQ_LEVEL;
 		else
 			desc->status = desc->status & ~IRQ_LEVEL;
-	break;
+		break;
 	case 2:
 		mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
 		if ((mfdcr(DCRN_UIC_TR(UIC2)) & (1 << (31 - bit))) == 0)
 			desc->status |= IRQ_LEVEL;
 		else
 			desc->status = desc->status & ~IRQ_LEVEL;
-	break;
+		break;
 	}
 
 }
@@ -269,6 +269,9 @@ ppc4xx_uic_end(unsigned int irq)
 	case 1:
 		tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
 		break;
+	case 2:
+		tr_bits = mfdcr(DCRN_UIC_TR(UIC2));
+		break;
 	}
 
 	if ((tr_bits & (1 << (31 - bit))) == 0) {

include/asm-ppc/reg.h

@@ -444,7 +444,7 @@
 #define PVR_440GP_RC2	0x40200481
 #define PVR_440GX_RA	0x51b21850
 #define PVR_440GX_RB	0x51b21851
-#define PVR_440GX_RB1	0x51b21852
+#define PVR_440GX_RC	0x51b21892
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000