Commit 254f9463 authored by Michael Turquette's avatar Michael Turquette

Merge branch 'clk-shmobile-for-v4.4' of...

Merge branch 'clk-shmobile-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
parents eae14465 9d0c3c68
* Renesas Clock Pulse Generator / Module Standby and Software Reset
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
and MSSR (Module Standby and Software Reset) blocks are intimately connected,
and share the same register block.
They provide the following functionalities:
- The CPG block generates various core clocks,
- The MSSR block provides two functions:
1. Module Standby, providing a Clock Domain to control the clock supply
to individual SoC devices,
2. Reset Control, to perform a software reset of individual SoC devices.
Required Properties:
- compatible: Must be one of:
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7795)
- "extalr" (r8a7795)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/*-cpg-mssr.h>.
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number, as defined in the datasheet.
- #power-domain-cells: Must be 0
- SoC devices that are part of the CPG/MSSR Clock Domain and can be
power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Examples
--------
- CPG device node:
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
};
- CPG/MSSR Clock Domain member device node:
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a7795", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>;
clock-names = "sci_ick";
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
status = "disabled";
};
/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7795 CPG Core Clocks */
#define R8A7795_CLK_Z 0
#define R8A7795_CLK_Z2 1
#define R8A7795_CLK_ZR 2
#define R8A7795_CLK_ZG 3
#define R8A7795_CLK_ZTR 4
#define R8A7795_CLK_ZTRD2 5
#define R8A7795_CLK_ZT 6
#define R8A7795_CLK_ZX 7
#define R8A7795_CLK_S0D1 8
#define R8A7795_CLK_S0D4 9
#define R8A7795_CLK_S1D1 10
#define R8A7795_CLK_S1D2 11
#define R8A7795_CLK_S1D4 12
#define R8A7795_CLK_S2D1 13
#define R8A7795_CLK_S2D2 14
#define R8A7795_CLK_S2D4 15
#define R8A7795_CLK_S3D1 16
#define R8A7795_CLK_S3D2 17
#define R8A7795_CLK_S3D4 18
#define R8A7795_CLK_LB 19
#define R8A7795_CLK_CL 20
#define R8A7795_CLK_ZB3 21
#define R8A7795_CLK_ZB3D2 22
#define R8A7795_CLK_CR 23
#define R8A7795_CLK_CRD2 24
#define R8A7795_CLK_SD0H 25
#define R8A7795_CLK_SD0 26
#define R8A7795_CLK_SD1H 27
#define R8A7795_CLK_SD1 28
#define R8A7795_CLK_SD2H 29
#define R8A7795_CLK_SD2 30
#define R8A7795_CLK_SD3H 31
#define R8A7795_CLK_SD3 32
#define R8A7795_CLK_SSP2 33
#define R8A7795_CLK_SSP1 34
#define R8A7795_CLK_SSPRS 35
#define R8A7795_CLK_RPC 36
#define R8A7795_CLK_RPCD2 37
#define R8A7795_CLK_MSO 38
#define R8A7795_CLK_CANFD 39
#define R8A7795_CLK_HDMI 40
#define R8A7795_CLK_CSI0 41
#define R8A7795_CLK_CSIREF 42
#define R8A7795_CLK_CP 43
#define R8A7795_CLK_CPEX 44
#define R8A7795_CLK_R 45
#define R8A7795_CLK_OSC 46
#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define CPG_CORE 0 /* Core Clock */
#define CPG_MOD 1 /* Module Clock */
#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
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