Commit 257505b8 authored by Caesar Wang's avatar Caesar Wang Committed by Greg Kroah-Hartman

arm: dts: rockchip: add reset node for the exist saradc SoCs

commit 3d4267a5 upstream.

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 09169bf4
......@@ -197,6 +197,8 @@ tsadc: tsadc@20060000 {
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
......
......@@ -279,6 +279,8 @@ saradc: saradc@ff100000 {
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
......
......@@ -399,6 +399,8 @@ saradc: saradc@2006c000 {
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
......
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