Commit 262af557 authored by Guo Chao's avatar Guo Chao Committed by Benjamin Herrenschmidt

powerpc/powernv: Enable M64 aperatus for PHB3

This patch enables M64 aperatus for PHB3.

We already had platform hook (ppc_md.pcibios_window_alignment) to affect
the PCI resource assignment done in PCI core so that each PE's M32 resource
was built on basis of M32 segment size. Similarly, we're using that for
M64 assignment on basis of M64 segment size.

   * We're using last M64 BAR to cover M64 aperatus, and it's shared by all
     256 PEs.
   * We don't support P7IOC yet. However, some function callbacks are added
     to (struct pnv_phb) so that we can reuse them on P7IOC in future.
   * PE, corresponding to PCI bus with large M64 BAR device attached, might
     span multiple M64 segments. We introduce "compound" PE to cover the case.
     The compound PE is a list of PEs and the master PE is used as before.
     The slave PEs are just for MMIO isolation.
Signed-off-by: default avatarGuo Chao <yan@linux.vnet.ibm.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent bb593c00
...@@ -340,6 +340,12 @@ enum OpalMveEnableAction { ...@@ -340,6 +340,12 @@ enum OpalMveEnableAction {
OPAL_ENABLE_MVE = 1 OPAL_ENABLE_MVE = 1
}; };
enum OpalM64EnableAction {
OPAL_DISABLE_M64 = 0,
OPAL_ENABLE_M64_SPLIT = 1,
OPAL_ENABLE_M64_NON_SPLIT = 2
};
enum OpalPciResetScope { enum OpalPciResetScope {
OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
...@@ -768,7 +774,7 @@ int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, ...@@ -768,7 +774,7 @@ int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
uint16_t window_num, uint16_t window_num,
uint64_t starting_real_address, uint64_t starting_real_address,
uint64_t starting_pci_address, uint64_t starting_pci_address,
uint16_t segment_size); uint64_t size);
int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
uint16_t window_type, uint16_t window_num, uint16_t window_type, uint16_t window_num,
uint16_t segment_num); uint16_t segment_num);
......
This diff is collapsed.
...@@ -21,6 +21,8 @@ enum pnv_phb_model { ...@@ -21,6 +21,8 @@ enum pnv_phb_model {
#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
/* Data associated with a PE, including IOMMU tracking etc.. */ /* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb; struct pnv_phb;
...@@ -64,6 +66,10 @@ struct pnv_ioda_pe { ...@@ -64,6 +66,10 @@ struct pnv_ioda_pe {
*/ */
int mve_number; int mve_number;
/* PEs in compound case */
struct pnv_ioda_pe *master;
struct list_head slaves;
/* Link in list of PE#s */ /* Link in list of PE#s */
struct list_head dma_link; struct list_head dma_link;
struct list_head list; struct list_head list;
...@@ -119,6 +125,9 @@ struct pnv_phb { ...@@ -119,6 +125,9 @@ struct pnv_phb {
void (*fixup_phb)(struct pci_controller *hose); void (*fixup_phb)(struct pci_controller *hose);
u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
void (*shutdown)(struct pnv_phb *phb); void (*shutdown)(struct pnv_phb *phb);
int (*init_m64)(struct pnv_phb *phb);
void (*alloc_m64_pe)(struct pnv_phb *phb);
int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
union { union {
struct { struct {
...@@ -129,9 +138,20 @@ struct pnv_phb { ...@@ -129,9 +138,20 @@ struct pnv_phb {
/* Global bridge info */ /* Global bridge info */
unsigned int total_pe; unsigned int total_pe;
unsigned int reserved_pe; unsigned int reserved_pe;
/* 32-bit MMIO window */
unsigned int m32_size; unsigned int m32_size;
unsigned int m32_segsize; unsigned int m32_segsize;
unsigned int m32_pci_base; unsigned int m32_pci_base;
/* 64-bit MMIO window */
unsigned int m64_bar_idx;
unsigned long m64_size;
unsigned long m64_segsize;
unsigned long m64_base;
unsigned long m64_bar_alloc;
/* IO ports */
unsigned int io_size; unsigned int io_size;
unsigned int io_segsize; unsigned int io_segsize;
unsigned int io_pci_base; unsigned int io_pci_base;
......
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