Commit 2703a668 authored by Avinash Patil's avatar Avinash Patil Committed by John W. Linville

mwifiex: support for event done interrupt

This patch adds support for writing CPU event interrupt done back
to device.
Patch also increases interrupt buffer ring size from 4 to 8.
Signed-off-by: default avatarAvinash Patil <patila@marvell.com>
Signed-off-by: default avatarCathy Luo <cluo@marvell.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3223db20
...@@ -1726,6 +1726,13 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) ...@@ -1726,6 +1726,13 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
buffer is released. This is just to make things simpler, buffer is released. This is just to make things simpler,
we need to find a better method of managing these buffers. we need to find a better method of managing these buffers.
*/ */
} else {
if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
CPU_INTR_EVENT_DONE)) {
dev_warn(adapter->dev,
"Write register failed\n");
return -1;
}
} }
return 0; return 0;
......
...@@ -40,8 +40,8 @@ ...@@ -40,8 +40,8 @@
#define MWIFIEX_TXBD_MASK 0x3F #define MWIFIEX_TXBD_MASK 0x3F
#define MWIFIEX_RXBD_MASK 0x3F #define MWIFIEX_RXBD_MASK 0x3F
#define MWIFIEX_MAX_EVT_BD 0x04 #define MWIFIEX_MAX_EVT_BD 0x08
#define MWIFIEX_EVTBD_MASK 0x07 #define MWIFIEX_EVTBD_MASK 0x0f
/* PCIE INTERNAL REGISTERS */ /* PCIE INTERNAL REGISTERS */
#define PCIE_SCRATCH_0_REG 0xC10 #define PCIE_SCRATCH_0_REG 0xC10
...@@ -69,6 +69,7 @@ ...@@ -69,6 +69,7 @@
#define CPU_INTR_DOOR_BELL BIT(1) #define CPU_INTR_DOOR_BELL BIT(1)
#define CPU_INTR_SLEEP_CFM_DONE BIT(2) #define CPU_INTR_SLEEP_CFM_DONE BIT(2)
#define CPU_INTR_RESET BIT(3) #define CPU_INTR_RESET BIT(3)
#define CPU_INTR_EVENT_DONE BIT(5)
#define HOST_INTR_DNLD_DONE BIT(0) #define HOST_INTR_DNLD_DONE BIT(0)
#define HOST_INTR_UPLD_RDY BIT(1) #define HOST_INTR_UPLD_RDY BIT(1)
......
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