Commit 28fae2d5 authored by Antoine Tenart's avatar Antoine Tenart Committed by Greg Kroah-Hartman

net: mvpp2: fix the number of queues per cpu for PPv2.2

[ Upstream commit 70afb58e ]

The Marvell PPv2.2 engine only has 8 Rx queues per CPU, while PPv2.1 has
16 of them. This patch updates the code so that the Rx queues mask width
is selected given the version of the network controller used.
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 0ede78b3
...@@ -253,7 +253,8 @@ ...@@ -253,7 +253,8 @@
#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \
((version) == MVPP21 ? 0xffff : 0xff)
#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16
#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
......
...@@ -908,7 +908,7 @@ static void mvpp2_interrupts_unmask(void *arg) ...@@ -908,7 +908,7 @@ static void mvpp2_interrupts_unmask(void *arg)
u32 val; u32 val;
val = MVPP2_CAUSE_MISC_SUM_MASK | val = MVPP2_CAUSE_MISC_SUM_MASK |
MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
if (port->has_tx_irqs) if (port->has_tx_irqs)
val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
...@@ -928,7 +928,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) ...@@ -928,7 +928,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
if (mask) if (mask)
val = 0; val = 0;
else else
val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
for (i = 0; i < port->nqvecs; i++) { for (i = 0; i < port->nqvecs; i++) {
struct mvpp2_queue_vector *v = port->qvecs + i; struct mvpp2_queue_vector *v = port->qvecs + i;
...@@ -3059,7 +3059,8 @@ static int mvpp2_poll(struct napi_struct *napi, int budget) ...@@ -3059,7 +3059,8 @@ static int mvpp2_poll(struct napi_struct *napi, int budget)
} }
/* Process RX packets */ /* Process RX packets */
cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; cause_rx = cause_rx_tx &
MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
cause_rx <<= qv->first_rxq; cause_rx <<= qv->first_rxq;
cause_rx |= qv->pending_cause_rx; cause_rx |= qv->pending_cause_rx;
while (cause_rx && budget > 0) { while (cause_rx && budget > 0) {
......
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