Commit 2cad26a9 authored by Yong Shen's avatar Yong Shen Committed by Sascha Hauer

ARM i.MX5 uart clock bug fix

uart clk is from pll3 on mx53 instead of mx51
Signed-off-by: default avatarYong Shen <yong.shen@freescale.com>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent b0a6ba5f
......@@ -1370,7 +1370,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
clk_tree_init();
clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
......@@ -1413,6 +1412,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
clk_tree_init();
clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
......
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