Commit 2dcfaf85 authored by Jiang Liu's avatar Jiang Liu Committed by Bjorn Helgaas

PCI/portdrv: Use PCI Express Capability accessors

Use PCI Express Capability access functions to simplify portdrv.
Signed-off-by: default avatarJiang Liu <jiang.liu@huawei.com>
Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
parent 028fbad4
...@@ -246,8 +246,7 @@ static void cleanup_service_irqs(struct pci_dev *dev) ...@@ -246,8 +246,7 @@ static void cleanup_service_irqs(struct pci_dev *dev)
*/ */
static int get_port_device_capability(struct pci_dev *dev) static int get_port_device_capability(struct pci_dev *dev)
{ {
int services = 0, pos; int services = 0;
u16 reg16;
u32 reg32; u32 reg32;
int cap_mask = 0; int cap_mask = 0;
int err; int err;
...@@ -265,11 +264,9 @@ static int get_port_device_capability(struct pci_dev *dev) ...@@ -265,11 +264,9 @@ static int get_port_device_capability(struct pci_dev *dev)
return 0; return 0;
} }
pos = pci_pcie_cap(dev);
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
/* Hot-Plug Capable */ /* Hot-Plug Capable */
if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) { if (cap_mask & PCIE_PORT_SERVICE_HP) {
pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, &reg32); pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, &reg32);
if (reg32 & PCI_EXP_SLTCAP_HPC) { if (reg32 & PCI_EXP_SLTCAP_HPC) {
services |= PCIE_PORT_SERVICE_HP; services |= PCIE_PORT_SERVICE_HP;
/* /*
...@@ -277,10 +274,8 @@ static int get_port_device_capability(struct pci_dev *dev) ...@@ -277,10 +274,8 @@ static int get_port_device_capability(struct pci_dev *dev)
* enabled by the BIOS and the hot-plug service driver * enabled by the BIOS and the hot-plug service driver
* is not loaded. * is not loaded.
*/ */
pos += PCI_EXP_SLTCTL; pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
pci_read_config_word(dev, pos, &reg16); PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
pci_write_config_word(dev, pos, reg16);
} }
} }
/* AER capable */ /* AER capable */
......
...@@ -64,14 +64,7 @@ __setup("pcie_ports=", pcie_port_setup); ...@@ -64,14 +64,7 @@ __setup("pcie_ports=", pcie_port_setup);
*/ */
void pcie_clear_root_pme_status(struct pci_dev *dev) void pcie_clear_root_pme_status(struct pci_dev *dev)
{ {
int rtsta_pos; pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
u32 rtsta;
rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
pci_read_config_dword(dev, rtsta_pos, &rtsta);
rtsta |= PCI_EXP_RTSTA_PME;
pci_write_config_dword(dev, rtsta_pos, rtsta);
} }
static int pcie_portdrv_restore_config(struct pci_dev *dev) static int pcie_portdrv_restore_config(struct pci_dev *dev)
......
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