Commit 32270e80 authored by Kevin Hilman's avatar Kevin Hilman

Merge tag 'armsoc-drivers' into test-merge

ARM: SoC: driver updates for v4.2

Some of these are for drivers/soc, where we're now putting
SoC-specific drivers these days. Some are for other driver subsystems
where we have received acks from the appropriate maintainers.

Some highlights:

- simple-mfd: document DT bindings and misc updates
- migrate mach-berlin to simple-mfd for clock, pinctrl and reset
- memory: support for Tegra132 SoC
- memory: introduce tegra EMC driver for scaling memory frequency
- misc. updates for ARM CCI and CCN busses

 Conflicts:
	arch/arm64/boot/dts/arm/juno-motherboard.dtsi

 Trivial add/add conflict with our dt branch.
 Resolution: take both sides.

# gpg: Signature made Wed Jun 24 21:32:17 2015 PDT using RSA key ID D3FBC665
# gpg: Good signature from "Kevin Hilman <khilman@deeprootsystems.com>"
# gpg:                 aka "Kevin Hilman <khilman@linaro.org>"
# gpg:                 aka "Kevin Hilman <khilman@kernel.org>"

# Conflicts:
#	arch/arm64/boot/dts/arm/juno-motherboard.dtsi
parents 39e79b87 4af34b57
...@@ -33,20 +33,23 @@ directory, with first 8 configurable by user and additional ...@@ -33,20 +33,23 @@ directory, with first 8 configurable by user and additional
Cycle counter is described by a "type" value 0xff and does Cycle counter is described by a "type" value 0xff and does
not require any other settings. not require any other settings.
The driver also provides a "cpumask" sysfs attribute, which contains
a single CPU ID, of the processor which will be used to handle all
the CCN PMU events. It is recommended that the user space tools
request the events on this processor (if not, the perf_event->cpu value
will be overwritten anyway). In case of this processor being offlined,
the events are migrated to another one and the attribute is updated.
Example of perf tool use: Example of perf tool use:
/ # perf list | grep ccn / # perf list | grep ccn
ccn/cycles/ [Kernel PMU event] ccn/cycles/ [Kernel PMU event]
<...> <...>
ccn/xp_valid_flit/ [Kernel PMU event] ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event]
<...> <...>
/ # perf stat -C 0 -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ / # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
sleep 1 sleep 1
The driver does not support sampling, therefore "perf record" will The driver does not support sampling, therefore "perf record" will
not work. Also notice that only single cpu is being selected not work. Per-task (without "-a") perf sessions are not supported.
("-C 0") - this is because perf framework does not support
"non-CPU related" counters (yet?) so system-wide session ("-a")
would try (and in most cases fail) to set up the same event
per each CPU.
...@@ -31,8 +31,9 @@ specific to ARM. ...@@ -31,8 +31,9 @@ specific to ARM.
- compatible - compatible
Usage: required Usage: required
Value type: <string> Value type: <string>
Definition: must be set to Definition: must contain one of the following:
"arm,cci-400" "arm,cci-400"
"arm,cci-500"
- reg - reg
Usage: required Usage: required
...@@ -99,6 +100,7 @@ specific to ARM. ...@@ -99,6 +100,7 @@ specific to ARM.
"arm,cci-400-pmu,r1" "arm,cci-400-pmu,r1"
"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
secure acces to CCI registers secure acces to CCI registers
"arm,cci-500-pmu,r0"
- reg: - reg:
Usage: required Usage: required
Value type: Integer cells. A register entry, expressed Value type: Integer cells. A register entry, expressed
......
NVIDIA Tegra Memory Controller device tree bindings NVIDIA Tegra Memory Controller device tree bindings
=================================================== ===================================================
memory-controller node
----------------------
Required properties: Required properties:
- compatible: Should be "nvidia,tegra<chip>-mc" - compatible: Should be "nvidia,tegra<chip>-mc"
- reg: Physical base address and length of the controller's registers. - reg: Physical base address and length of the controller's registers.
...@@ -15,9 +18,49 @@ Required properties: ...@@ -15,9 +18,49 @@ Required properties:
This device implements an IOMMU that complies with the generic IOMMU binding. This device implements an IOMMU that complies with the generic IOMMU binding.
See ../iommu/iommu.txt for details. See ../iommu/iommu.txt for details.
Example: emc-timings subnode
-------- -------------------
The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
register PMC_STRAPPING_OPT_A).
Required properties for "emc-timings" nodes :
- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
timing subnode
--------------
Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
Required properties for timing nodes :
- clock-frequency : Should contain the memory clock rate in Hz.
- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
specified, according to the board documentation:
MC_EMEM_ARB_CFG
MC_EMEM_ARB_OUTSTANDING_REQ
MC_EMEM_ARB_TIMING_RCD
MC_EMEM_ARB_TIMING_RP
MC_EMEM_ARB_TIMING_RC
MC_EMEM_ARB_TIMING_RAS
MC_EMEM_ARB_TIMING_FAW
MC_EMEM_ARB_TIMING_RRD
MC_EMEM_ARB_TIMING_RAP2PRE
MC_EMEM_ARB_TIMING_WAP2PRE
MC_EMEM_ARB_TIMING_R2R
MC_EMEM_ARB_TIMING_W2W
MC_EMEM_ARB_TIMING_R2W
MC_EMEM_ARB_TIMING_W2R
MC_EMEM_ARB_DA_TURNS
MC_EMEM_ARB_DA_COVERS
MC_EMEM_ARB_MISC0
MC_EMEM_ARB_MISC1
MC_EMEM_ARB_RING1_THROTTLE
Example SoC include file:
/ {
mc: memory-controller@0,70019000 { mc: memory-controller@0,70019000 {
compatible = "nvidia,tegra124-mc"; compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>; reg = <0x0 0x70019000 0x0 0x1000>;
...@@ -34,3 +77,40 @@ Example: ...@@ -34,3 +77,40 @@ Example:
... ...
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
}; };
};
Example board file:
/ {
memory-controller@0,70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 /* MC_EMEM_ARB_CFG */
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0x77e30303 /* MC_EMEM_ARB_MISC0 */
0x70000f03 /* MC_EMEM_ARB_MISC1 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};
};
Multi-Function Devices (MFD)
These devices comprise a nexus for heterogeneous hardware blocks containing
more than one non-unique yet varying hardware functionality.
A typical MFD can be:
- A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
Integrated Circuit) that is manufactured in a lower technology node (rough
silicon) that handles analog drivers for things like audio amplifiers, LED
drivers, level shifters, PHY (physical interfaces to things like USB or
ethernet), regulators etc.
- A range of memory registers containing "miscellaneous system registers" also
known as a system controller "syscon" or any other memory range containing a
mix of unrelated hardware devices.
Optional properties:
- compatible : "simple-mfd" - this signifies that the operating system should
consider all subnodes of the MFD device as separate devices akin to how
"simple-bus" inidicates when to see subnodes as children for a simple
memory-mapped bus. For more complex devices, when the nexus driver has to
probe registers to figure out what child devices exist etc, this should not
be used. In the latter case the child devices will be determined by the
operating system.
Example:
foo@1000 {
compatible = "syscon", "simple-mfd";
reg = <0x01000 0x1000>;
led@08.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
label = "myled";
default-state = "on";
};
};
...@@ -10,3 +10,5 @@ Required properties: ...@@ -10,3 +10,5 @@ Required properties:
The second entry gives the physical address and length of the The second entry gives the physical address and length of the
registers indicating the strapping options. registers indicating the strapping options.
Optional properties:
- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
Allwinnner SoC SRAM controllers
-----------------------------------------------------
The SRAM controller found on most Allwinner devices is represented by
a regular node for the SRAM controller itself, with sub-nodes
reprensenting the SRAM handled by the SRAM controller.
Controller Node
---------------
Required properties:
- compatible : "allwinner,sun4i-a10-sram-controller"
- reg : sram controller register offset + length
SRAM nodes
----------
Each SRAM is described using the mmio-sram bindings documented in
Documentation/devicetree/bindings/misc/sram.txt
Each SRAM will have SRAM sections that are going to be handled by the
SRAM controller as subnodes. These sections are represented following
once again the representation described in the mmio-sram binding.
The valid sections compatible are:
- allwinner,sun4i-a10-sram-a3-a4
- allwinner,sun4i-a10-sram-d
Devices using SRAM sections
---------------------------
Some devices need to request to the SRAM controller to map an SRAM for
their exclusive use.
The relationship between such a device and an SRAM section is
expressed through the allwinner,sram property, that will take a
phandle and an argument.
This valid values for this argument are:
- 0: CPU
- 1: Device
Example
-------
sram-controller@01c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_a: sram@00000000 {
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
emac_sram: sram-section@8000 {
compatible = "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
};
};
emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-a10-emac";
...
allwinner,sram = <&emac_sram 1>;
};
...@@ -114,7 +114,7 @@ soc { ...@@ -114,7 +114,7 @@ soc {
ranges; ranges;
syscon: syscon@10000000 { syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon"; compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>; reg = <0x10000000 0x1000>;
led@08.0 { led@08.0 {
......
...@@ -84,7 +84,7 @@ soc { ...@@ -84,7 +84,7 @@ soc {
sdhci0: sdhci@ab0000 { sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>; reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
clock-names = "io", "core"; clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
...@@ -93,7 +93,7 @@ sdhci0: sdhci@ab0000 { ...@@ -93,7 +93,7 @@ sdhci0: sdhci@ab0000 {
sdhci1: sdhci@ab0800 { sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>; reg = <0xab0800 0x200>;
clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
clock-names = "io", "core"; clock-names = "io", "core";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
...@@ -103,7 +103,7 @@ sdhci2: sdhci@ab1000 { ...@@ -103,7 +103,7 @@ sdhci2: sdhci@ab1000 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>; reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
clock-names = "io", "core"; clock-names = "io", "core";
pinctrl-0 = <&emmc_pmux>; pinctrl-0 = <&emmc_pmux>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -133,13 +133,13 @@ local-timer@ad0600 { ...@@ -133,13 +133,13 @@ local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>; reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&chip CLKID_TWD>; clocks = <&chip_clk CLKID_TWD>;
}; };
eth1: ethernet@b90000 { eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth"; compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>; reg = <0xb90000 0x10000>;
clocks = <&chip CLKID_GETH1>; clocks = <&chip_clk CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */ /* set by bootloader */
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
...@@ -162,7 +162,7 @@ cpu-ctrl@dd0000 { ...@@ -162,7 +162,7 @@ cpu-ctrl@dd0000 {
eth0: ethernet@e50000 { eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth"; compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>; reg = <0xe50000 0x10000>;
clocks = <&chip CLKID_GETH0>; clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */ /* set by bootloader */
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
...@@ -261,7 +261,7 @@ timer0: timer@2c00 { ...@@ -261,7 +261,7 @@ timer0: timer@2c00 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>; reg = <0x2c00 0x14>;
interrupts = <8>; interrupts = <8>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "okay"; status = "okay";
}; };
...@@ -270,7 +270,7 @@ timer1: timer@2c14 { ...@@ -270,7 +270,7 @@ timer1: timer@2c14 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>; reg = <0x2c14 0x14>;
interrupts = <9>; interrupts = <9>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "okay"; status = "okay";
}; };
...@@ -279,7 +279,7 @@ timer2: timer@2c28 { ...@@ -279,7 +279,7 @@ timer2: timer@2c28 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>; reg = <0x2c28 0x14>;
interrupts = <10>; interrupts = <10>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -288,7 +288,7 @@ timer3: timer@2c3c { ...@@ -288,7 +288,7 @@ timer3: timer@2c3c {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>; reg = <0x2c3c 0x14>;
interrupts = <11>; interrupts = <11>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -297,7 +297,7 @@ timer4: timer@2c50 { ...@@ -297,7 +297,7 @@ timer4: timer@2c50 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>; reg = <0x2c50 0x14>;
interrupts = <12>; interrupts = <12>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -306,7 +306,7 @@ timer5: timer@2c64 { ...@@ -306,7 +306,7 @@ timer5: timer@2c64 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>; reg = <0x2c64 0x14>;
interrupts = <13>; interrupts = <13>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -315,7 +315,7 @@ timer6: timer@2c78 { ...@@ -315,7 +315,7 @@ timer6: timer@2c78 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>; reg = <0x2c78 0x14>;
interrupts = <14>; interrupts = <14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -324,7 +324,7 @@ timer7: timer@2c8c { ...@@ -324,7 +324,7 @@ timer7: timer@2c8c {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>; reg = <0x2c8c 0x14>;
interrupts = <15>; interrupts = <15>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -343,7 +343,7 @@ ahci: sata@e90000 { ...@@ -343,7 +343,7 @@ ahci: sata@e90000 {
compatible = "marvell,berlin2-ahci", "generic-ahci"; compatible = "marvell,berlin2-ahci", "generic-ahci";
reg = <0xe90000 0x1000>; reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SATA>; clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -363,7 +363,7 @@ sata1: sata-port@1 { ...@@ -363,7 +363,7 @@ sata1: sata-port@1 {
sata_phy: phy@e900a0 { sata_phy: phy@e900a0 {
compatible = "marvell,berlin2-sata-phy"; compatible = "marvell,berlin2-sata-phy";
reg = <0xe900a0 0x200>; reg = <0xe900a0 0x200>;
clocks = <&chip CLKID_SATA>; clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
#phy-cells = <1>; #phy-cells = <1>;
...@@ -379,16 +379,28 @@ sata-phy@1 { ...@@ -379,16 +379,28 @@ sata-phy@1 {
}; };
chip: chip-control@ea0000 { chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl"; compatible = "simple-mfd", "syscon";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>; reg = <0xea0000 0x400>;
clocks = <&refclk>;
clock-names = "refclk";
emmc_pmux: emmc-pmux { chip_clk: clock {
groups = "G26"; compatible = "marvell,berlin2-clk";
function = "emmc"; #clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2-soc-pinctrl";
emmc_pmux: emmc-pmux {
groups = "G26";
function = "emmc";
};
};
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
}; };
}; };
...@@ -470,22 +482,24 @@ uart2: serial@b000 { ...@@ -470,22 +482,24 @@ uart2: serial@b000 {
}; };
sysctrl: system-controller@d000 { sysctrl: system-controller@d000 {
compatible = "marvell,berlin2-system-ctrl"; compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>; reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux { sys_pinctrl: pin-controller {
groups = "GSM4"; compatible = "marvell,berlin2-system-pinctrl";
function = "uart0"; uart0_pmux: uart0-pmux {
}; groups = "GSM4";
function = "uart0";
uart1_pmux: uart1-pmux { };
groups = "GSM5";
function = "uart1"; uart1_pmux: uart1-pmux {
}; groups = "GSM5";
function = "uart1";
uart2_pmux: uart2-pmux { };
groups = "GSM3"; uart2_pmux: uart2-pmux {
function = "uart2"; groups = "GSM3";
function = "uart2";
};
}; };
}; };
......
...@@ -81,7 +81,7 @@ pmu { ...@@ -81,7 +81,7 @@ pmu {
sdhci0: sdhci@ab0000 { sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>; reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
clock-names = "io", "core"; clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
...@@ -105,14 +105,14 @@ local-timer@ad0600 { ...@@ -105,14 +105,14 @@ local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>; reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&chip CLKID_TWD>; clocks = <&chip_clk CLKID_TWD>;
}; };
usb_phy0: usb-phy@b74000 { usb_phy0: usb-phy@b74000 {
compatible = "marvell,berlin2cd-usb-phy"; compatible = "marvell,berlin2cd-usb-phy";
reg = <0xb74000 0x128>; reg = <0xb74000 0x128>;
#phy-cells = <0>; #phy-cells = <0>;
resets = <&chip 0x178 23>; resets = <&chip_rst 0x178 23>;
status = "disabled"; status = "disabled";
}; };
...@@ -120,14 +120,14 @@ usb_phy1: usb-phy@b78000 { ...@@ -120,14 +120,14 @@ usb_phy1: usb-phy@b78000 {
compatible = "marvell,berlin2cd-usb-phy"; compatible = "marvell,berlin2cd-usb-phy";
reg = <0xb78000 0x128>; reg = <0xb78000 0x128>;
#phy-cells = <0>; #phy-cells = <0>;
resets = <&chip 0x178 24>; resets = <&chip_rst 0x178 24>;
status = "disabled"; status = "disabled";
}; };
eth1: ethernet@b90000 { eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth"; compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>; reg = <0xb90000 0x10000>;
clocks = <&chip CLKID_GETH1>; clocks = <&chip_clk CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */ /* set by bootloader */
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
...@@ -145,7 +145,7 @@ ethphy1: ethernet-phy@0 { ...@@ -145,7 +145,7 @@ ethphy1: ethernet-phy@0 {
eth0: ethernet@e50000 { eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth"; compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>; reg = <0xe50000 0x10000>;
clocks = <&chip CLKID_GETH0>; clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */ /* set by bootloader */
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
...@@ -244,7 +244,7 @@ timer0: timer@2c00 { ...@@ -244,7 +244,7 @@ timer0: timer@2c00 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>; reg = <0x2c00 0x14>;
interrupts = <8>; interrupts = <8>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "okay"; status = "okay";
}; };
...@@ -253,7 +253,7 @@ timer1: timer@2c14 { ...@@ -253,7 +253,7 @@ timer1: timer@2c14 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>; reg = <0x2c14 0x14>;
interrupts = <9>; interrupts = <9>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "okay"; status = "okay";
}; };
...@@ -262,7 +262,7 @@ timer2: timer@2c28 { ...@@ -262,7 +262,7 @@ timer2: timer@2c28 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>; reg = <0x2c28 0x14>;
interrupts = <10>; interrupts = <10>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -271,7 +271,7 @@ timer3: timer@2c3c { ...@@ -271,7 +271,7 @@ timer3: timer@2c3c {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>; reg = <0x2c3c 0x14>;
interrupts = <11>; interrupts = <11>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -280,7 +280,7 @@ timer4: timer@2c50 { ...@@ -280,7 +280,7 @@ timer4: timer@2c50 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>; reg = <0x2c50 0x14>;
interrupts = <12>; interrupts = <12>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -289,7 +289,7 @@ timer5: timer@2c64 { ...@@ -289,7 +289,7 @@ timer5: timer@2c64 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>; reg = <0x2c64 0x14>;
interrupts = <13>; interrupts = <13>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -298,7 +298,7 @@ timer6: timer@2c78 { ...@@ -298,7 +298,7 @@ timer6: timer@2c78 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>; reg = <0x2c78 0x14>;
interrupts = <14>; interrupts = <14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -307,7 +307,7 @@ timer7: timer@2c8c { ...@@ -307,7 +307,7 @@ timer7: timer@2c8c {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>; reg = <0x2c8c 0x14>;
interrupts = <15>; interrupts = <15>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -323,16 +323,28 @@ aic: interrupt-controller@3000 { ...@@ -323,16 +323,28 @@ aic: interrupt-controller@3000 {
}; };
chip: chip-control@ea0000 { chip: chip-control@ea0000 {
compatible = "marvell,berlin2cd-chip-ctrl"; compatible = "simple-mfd", "syscon";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>; reg = <0xea0000 0x400>;
clocks = <&refclk>;
clock-names = "refclk";
uart0_pmux: uart0-pmux { chip_clk: clock {
groups = "G6"; compatible = "marvell,berlin2-clk";
function = "uart0"; #clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2cd-soc-pinctrl";
uart0_pmux: uart0-pmux {
groups = "G6";
function = "uart0";
};
};
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
}; };
}; };
...@@ -340,7 +352,7 @@ usb0: usb@ed0000 { ...@@ -340,7 +352,7 @@ usb0: usb@ed0000 {
compatible = "chipidea,usb2"; compatible = "chipidea,usb2";
reg = <0xed0000 0x200>; reg = <0xed0000 0x200>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_USB0>; clocks = <&chip_clk CLKID_USB0>;
phys = <&usb_phy0>; phys = <&usb_phy0>;
phy-names = "usb-phy"; phy-names = "usb-phy";
status = "disabled"; status = "disabled";
...@@ -350,7 +362,7 @@ usb1: usb@ee0000 { ...@@ -350,7 +362,7 @@ usb1: usb@ee0000 {
compatible = "chipidea,usb2"; compatible = "chipidea,usb2";
reg = <0xee0000 0x200>; reg = <0xee0000 0x200>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_USB1>; clocks = <&chip_clk CLKID_USB1>;
phys = <&usb_phy1>; phys = <&usb_phy1>;
phy-names = "usb-phy"; phy-names = "usb-phy";
status = "disabled"; status = "disabled";
...@@ -417,8 +429,12 @@ uart1: serial@a000 { ...@@ -417,8 +429,12 @@ uart1: serial@a000 {
}; };
sysctrl: system-controller@d000 { sysctrl: system-controller@d000 {
compatible = "marvell,berlin2cd-system-ctrl"; compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>; reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
compatible = "marvell,berlin2cd-system-pinctrl";
};
}; };
sic: interrupt-controller@e000 { sic: interrupt-controller@e000 {
......
...@@ -102,7 +102,7 @@ pmu { ...@@ -102,7 +102,7 @@ pmu {
sdhci0: sdhci@ab0000 { sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>; reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO1XIN>; clocks = <&chip_clk CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
...@@ -110,7 +110,7 @@ sdhci0: sdhci@ab0000 { ...@@ -110,7 +110,7 @@ sdhci0: sdhci@ab0000 {
sdhci1: sdhci@ab0800 { sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>; reg = <0xab0800 0x200>;
clocks = <&chip CLKID_SDIO1XIN>; clocks = <&chip_clk CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
...@@ -119,7 +119,7 @@ sdhci2: sdhci@ab1000 { ...@@ -119,7 +119,7 @@ sdhci2: sdhci@ab1000 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>; reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
clock-names = "io", "core"; clock-names = "io", "core";
status = "disabled"; status = "disabled";
}; };
...@@ -140,7 +140,7 @@ scu: snoop-control-unit@ad0000 { ...@@ -140,7 +140,7 @@ scu: snoop-control-unit@ad0000 {
local-timer@ad0600 { local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>; reg = <0xad0600 0x20>;
clocks = <&chip CLKID_TWD>; clocks = <&chip_clk CLKID_TWD>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
...@@ -155,7 +155,7 @@ usb_phy2: phy@a2f400 { ...@@ -155,7 +155,7 @@ usb_phy2: phy@a2f400 {
compatible = "marvell,berlin2-usb-phy"; compatible = "marvell,berlin2-usb-phy";
reg = <0xa2f400 0x128>; reg = <0xa2f400 0x128>;
#phy-cells = <0>; #phy-cells = <0>;
resets = <&chip 0x104 14>; resets = <&chip_rst 0x104 14>;
status = "disabled"; status = "disabled";
}; };
...@@ -163,7 +163,7 @@ usb2: usb@a30000 { ...@@ -163,7 +163,7 @@ usb2: usb@a30000 {
compatible = "chipidea,usb2"; compatible = "chipidea,usb2";
reg = <0xa30000 0x10000>; reg = <0xa30000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_USB2>; clocks = <&chip_clk CLKID_USB2>;
phys = <&usb_phy2>; phys = <&usb_phy2>;
phy-names = "usb-phy"; phy-names = "usb-phy";
status = "disabled"; status = "disabled";
...@@ -173,7 +173,7 @@ usb_phy0: phy@b74000 { ...@@ -173,7 +173,7 @@ usb_phy0: phy@b74000 {
compatible = "marvell,berlin2-usb-phy"; compatible = "marvell,berlin2-usb-phy";
reg = <0xb74000 0x128>; reg = <0xb74000 0x128>;
#phy-cells = <0>; #phy-cells = <0>;
resets = <&chip 0x104 12>; resets = <&chip_rst 0x104 12>;
status = "disabled"; status = "disabled";
}; };
...@@ -181,14 +181,14 @@ usb_phy1: phy@b78000 { ...@@ -181,14 +181,14 @@ usb_phy1: phy@b78000 {
compatible = "marvell,berlin2-usb-phy"; compatible = "marvell,berlin2-usb-phy";
reg = <0xb78000 0x128>; reg = <0xb78000 0x128>;
#phy-cells = <0>; #phy-cells = <0>;
resets = <&chip 0x104 13>; resets = <&chip_rst 0x104 13>;
status = "disabled"; status = "disabled";
}; };
eth0: ethernet@b90000 { eth0: ethernet@b90000 {
compatible = "marvell,pxa168-eth"; compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>; reg = <0xb90000 0x10000>;
clocks = <&chip CLKID_GETH0>; clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */ /* set by bootloader */
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
...@@ -295,7 +295,7 @@ i2c0: i2c@1400 { ...@@ -295,7 +295,7 @@ i2c0: i2c@1400 {
reg = <0x1400 0x100>; reg = <0x1400 0x100>;
interrupt-parent = <&aic>; interrupt-parent = <&aic>;
interrupts = <4>; interrupts = <4>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
pinctrl-0 = <&twsi0_pmux>; pinctrl-0 = <&twsi0_pmux>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "disabled"; status = "disabled";
...@@ -308,7 +308,7 @@ i2c1: i2c@1800 { ...@@ -308,7 +308,7 @@ i2c1: i2c@1800 {
reg = <0x1800 0x100>; reg = <0x1800 0x100>;
interrupt-parent = <&aic>; interrupt-parent = <&aic>;
interrupts = <5>; interrupts = <5>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
pinctrl-0 = <&twsi1_pmux>; pinctrl-0 = <&twsi1_pmux>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "disabled"; status = "disabled";
...@@ -317,7 +317,7 @@ i2c1: i2c@1800 { ...@@ -317,7 +317,7 @@ i2c1: i2c@1800 {
timer0: timer@2c00 { timer0: timer@2c00 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>; reg = <0x2c00 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
interrupts = <8>; interrupts = <8>;
}; };
...@@ -325,14 +325,14 @@ timer0: timer@2c00 { ...@@ -325,14 +325,14 @@ timer0: timer@2c00 {
timer1: timer@2c14 { timer1: timer@2c14 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>; reg = <0x2c14 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
}; };
timer2: timer@2c28 { timer2: timer@2c28 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>; reg = <0x2c28 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -340,7 +340,7 @@ timer2: timer@2c28 { ...@@ -340,7 +340,7 @@ timer2: timer@2c28 {
timer3: timer@2c3c { timer3: timer@2c3c {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>; reg = <0x2c3c 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -348,7 +348,7 @@ timer3: timer@2c3c { ...@@ -348,7 +348,7 @@ timer3: timer@2c3c {
timer4: timer@2c50 { timer4: timer@2c50 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>; reg = <0x2c50 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -356,7 +356,7 @@ timer4: timer@2c50 { ...@@ -356,7 +356,7 @@ timer4: timer@2c50 {
timer5: timer@2c64 { timer5: timer@2c64 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>; reg = <0x2c64 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -364,7 +364,7 @@ timer5: timer@2c64 { ...@@ -364,7 +364,7 @@ timer5: timer@2c64 {
timer6: timer@2c78 { timer6: timer@2c78 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>; reg = <0x2c78 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -372,7 +372,7 @@ timer6: timer@2c78 { ...@@ -372,7 +372,7 @@ timer6: timer@2c78 {
timer7: timer@2c8c { timer7: timer@2c8c {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>; reg = <0x2c8c 0x14>;
clocks = <&chip CLKID_CFG>; clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer"; clock-names = "timer";
status = "disabled"; status = "disabled";
}; };
...@@ -388,21 +388,33 @@ aic: interrupt-controller@3800 { ...@@ -388,21 +388,33 @@ aic: interrupt-controller@3800 {
}; };
chip: chip-control@ea0000 { chip: chip-control@ea0000 {
compatible = "marvell,berlin2q-chip-ctrl"; compatible = "simple-mfd", "syscon";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0xea0000 0x400>, <0xdd0170 0x10>; reg = <0xea0000 0x400>, <0xdd0170 0x10>;
clocks = <&refclk>;
clock-names = "refclk";
twsi0_pmux: twsi0-pmux { chip_clk: clock {
groups = "G6"; compatible = "marvell,berlin2q-clk";
function = "twsi0"; #clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
}; };
twsi1_pmux: twsi1-pmux { soc_pinctrl: pin-controller {
groups = "G7"; compatible = "marvell,berlin2q-soc-pinctrl";
function = "twsi1";
twsi0_pmux: twsi0-pmux {
groups = "G6";
function = "twsi0";
};
twsi1_pmux: twsi1-pmux {
groups = "G7";
function = "twsi1";
};
};
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
}; };
}; };
...@@ -410,7 +422,7 @@ ahci: sata@e90000 { ...@@ -410,7 +422,7 @@ ahci: sata@e90000 {
compatible = "marvell,berlin2q-ahci", "generic-ahci"; compatible = "marvell,berlin2q-ahci", "generic-ahci";
reg = <0xe90000 0x1000>; reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SATA>; clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -430,7 +442,7 @@ sata1: sata-port@1 { ...@@ -430,7 +442,7 @@ sata1: sata-port@1 {
sata_phy: phy@e900a0 { sata_phy: phy@e900a0 {
compatible = "marvell,berlin2q-sata-phy"; compatible = "marvell,berlin2q-sata-phy";
reg = <0xe900a0 0x200>; reg = <0xe900a0 0x200>;
clocks = <&chip CLKID_SATA>; clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
#phy-cells = <1>; #phy-cells = <1>;
...@@ -449,7 +461,7 @@ usb0: usb@ed0000 { ...@@ -449,7 +461,7 @@ usb0: usb@ed0000 {
compatible = "chipidea,usb2"; compatible = "chipidea,usb2";
reg = <0xed0000 0x10000>; reg = <0xed0000 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_USB0>; clocks = <&chip_clk CLKID_USB0>;
phys = <&usb_phy0>; phys = <&usb_phy0>;
phy-names = "usb-phy"; phy-names = "usb-phy";
status = "disabled"; status = "disabled";
...@@ -459,7 +471,7 @@ usb1: usb@ee0000 { ...@@ -459,7 +471,7 @@ usb1: usb@ee0000 {
compatible = "chipidea,usb2"; compatible = "chipidea,usb2";
reg = <0xee0000 0x10000>; reg = <0xee0000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_USB1>; clocks = <&chip_clk CLKID_USB1>;
phys = <&usb_phy1>; phys = <&usb_phy1>;
phy-names = "usb-phy"; phy-names = "usb-phy";
status = "disabled"; status = "disabled";
...@@ -554,27 +566,37 @@ porte: gpio-port@4 { ...@@ -554,27 +566,37 @@ porte: gpio-port@4 {
}; };
sysctrl: pin-controller@d000 { sysctrl: pin-controller@d000 {
compatible = "marvell,berlin2q-system-ctrl"; compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>; reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux { sys_pinctrl: pin-controller {
groups = "GSM12"; compatible = "marvell,berlin2q-system-pinctrl";
function = "uart0";
};
uart1_pmux: uart1-pmux { uart0_pmux: uart0-pmux {
groups = "GSM14"; groups = "GSM12";
function = "uart1"; function = "uart0";
}; };
uart1_pmux: uart1-pmux {
groups = "GSM14";
function = "uart1";
};
twsi2_pmux: twsi2-pmux {
groups = "GSM13";
function = "twsi2";
};
twsi2_pmux: twsi2-pmux { twsi3_pmux: twsi3-pmux {
groups = "GSM13"; groups = "GSM14";
function = "twsi2"; function = "twsi3";
};
}; };
twsi3_pmux: twsi3-pmux { adc: adc {
groups = "GSM14"; compatible = "marvell,berlin2-adc";
function = "twsi3"; interrupts = <12>, <14>;
interrupt-names = "adc", "tsen";
}; };
}; };
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
/ { / {
core-module@10000000 { core-module@10000000 {
compatible = "arm,core-module-integrator", "syscon"; compatible = "arm,core-module-integrator", "syscon", "simple-mfd";
reg = <0x10000000 0x200>; reg = <0x10000000 0x200>;
/* Use core module LED to indicate CPU load */ /* Use core module LED to indicate CPU load */
...@@ -95,7 +95,7 @@ kmi@19000000 { ...@@ -95,7 +95,7 @@ kmi@19000000 {
syscon { syscon {
/* Debug registers mapped as syscon */ /* Debug registers mapped as syscon */
compatible = "syscon"; compatible = "syscon", "simple-mfd";
reg = <0x1a000000 0x10>; reg = <0x1a000000 0x10>;
led@04.0 { led@04.0 {
......
...@@ -6,6 +6,7 @@ menuconfig ARCH_BERLIN ...@@ -6,6 +6,7 @@ menuconfig ARCH_BERLIN
select DW_APB_ICTL select DW_APB_ICTL
select DW_APB_TIMER_OF select DW_APB_TIMER_OF
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select MFD_SYSCON
select PINCTRL select PINCTRL
if ARCH_BERLIN if ARCH_BERLIN
......
...@@ -138,6 +138,74 @@ v2m_sysctl: sysctl@020000 { ...@@ -138,6 +138,74 @@ v2m_sysctl: sysctl@020000 {
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
}; };
apbregs@010000 {
compatible = "syscon", "simple-mfd";
reg = <0x010000 0x1000>;
led@08.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
label = "vexpress:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
label = "vexpress:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
label = "vexpress:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "vexpress:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
led@08.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "vexpress:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
led@08.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "vexpress:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
led@08.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "vexpress:6";
default-state = "off";
};
led@08.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "vexpress:7";
default-state = "off";
};
};
mmci@050000 { mmci@050000 {
compatible = "arm,pl180", "arm,primecell"; compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>; reg = <0x050000 0x1000>;
......
...@@ -139,6 +139,12 @@ CONFIG_MMC_ARMMMCI=y ...@@ -139,6 +139,12 @@ CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SPI=y CONFIG_MMC_SPI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_XGENE=y
......
...@@ -7,21 +7,24 @@ menu "Bus devices" ...@@ -7,21 +7,24 @@ menu "Bus devices"
config ARM_CCI config ARM_CCI
bool bool
config ARM_CCI_PMU
bool
select ARM_CCI
config ARM_CCI400_COMMON config ARM_CCI400_COMMON
bool bool
select ARM_CCI select ARM_CCI
config ARM_CCI400_PMU config ARM_CCI400_PMU
bool "ARM CCI400 PMU support" bool "ARM CCI400 PMU support"
default y depends on (ARM && CPU_V7) || ARM64
depends on ARM || ARM64 depends on PERF_EVENTS
depends on HW_PERF_EVENTS
select ARM_CCI400_COMMON select ARM_CCI400_COMMON
select ARM_CCI_PMU
help help
Support for PMU events monitoring on the ARM CCI cache coherent Support for PMU events monitoring on the ARM CCI-400 (cache coherent
interconnect. interconnect). CCI-400 supports counting events related to the
connected slave/master interfaces.
If unsure, say Y
config ARM_CCI400_PORT_CTRL config ARM_CCI400_PORT_CTRL
bool bool
...@@ -31,6 +34,20 @@ config ARM_CCI400_PORT_CTRL ...@@ -31,6 +34,20 @@ config ARM_CCI400_PORT_CTRL
Low level power management driver for CCI400 cache coherent Low level power management driver for CCI400 cache coherent
interconnect for ARM platforms. interconnect for ARM platforms.
config ARM_CCI500_PMU
bool "ARM CCI500 PMU support"
default y
depends on (ARM && CPU_V7) || ARM64
depends on PERF_EVENTS
select ARM_CCI_PMU
help
Support for PMU events monitoring on the ARM CCI-500 cache coherent
interconnect. CCI-500 provides 8 independent event counters, which
can count events pertaining to the slave/master interfaces as well
as the internal events to the CCI.
If unsure, say Y
config ARM_CCN config ARM_CCN
bool "ARM CCN driver support" bool "ARM CCN driver support"
depends on ARM || ARM64 depends on ARM || ARM64
......
This diff is collapsed.
This diff is collapsed.
...@@ -57,6 +57,7 @@ ...@@ -57,6 +57,7 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/log2.h> #include <linux/log2.h>
#include <linux/memblock.h>
#include <linux/syscore_ops.h> #include <linux/syscore_ops.h>
/* /*
...@@ -152,13 +153,39 @@ struct mvebu_mbus_state { ...@@ -152,13 +153,39 @@ struct mvebu_mbus_state {
static struct mvebu_mbus_state mbus_state; static struct mvebu_mbus_state mbus_state;
/*
* We provide two variants of the mv_mbus_dram_info() function:
*
* - The normal one, where the described DRAM ranges may overlap with
* the I/O windows, but for which the DRAM ranges are guaranteed to
* have a power of two size. Such ranges are suitable for the DMA
* masters that only DMA between the RAM and the device, which is
* actually all devices except the crypto engines.
*
* - The 'nooverlap' one, where the described DRAM ranges are
* guaranteed to not overlap with the I/O windows, but for which the
* DRAM ranges will not have power of two sizes. They will only be
* aligned on a 64 KB boundary, and have a size multiple of 64
* KB. Such ranges are suitable for the DMA masters that DMA between
* the crypto SRAM (which is mapped through an I/O window) and a
* device. This is the case for the crypto engines.
*/
static struct mbus_dram_target_info mvebu_mbus_dram_info; static struct mbus_dram_target_info mvebu_mbus_dram_info;
static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
const struct mbus_dram_target_info *mv_mbus_dram_info(void) const struct mbus_dram_target_info *mv_mbus_dram_info(void)
{ {
return &mvebu_mbus_dram_info; return &mvebu_mbus_dram_info;
} }
EXPORT_SYMBOL_GPL(mv_mbus_dram_info); EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
{
return &mvebu_mbus_dram_info_nooverlap;
}
EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
/* Checks whether the given window has remap capability */ /* Checks whether the given window has remap capability */
static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus, static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
const int win) const int win)
...@@ -576,6 +603,95 @@ static unsigned int armada_xp_mbus_win_remap_offset(int win) ...@@ -576,6 +603,95 @@ static unsigned int armada_xp_mbus_win_remap_offset(int win)
return MVEBU_MBUS_NO_REMAP; return MVEBU_MBUS_NO_REMAP;
} }
/*
* Use the memblock information to find the MBus bridge hole in the
* physical address space.
*/
static void __init
mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
{
struct memblock_region *r;
uint64_t s = 0;
for_each_memblock(memory, r) {
/*
* This part of the memory is above 4 GB, so we don't
* care for the MBus bridge hole.
*/
if (r->base >= 0x100000000ULL)
continue;
/*
* The MBus bridge hole is at the end of the RAM under
* the 4 GB limit.
*/
if (r->base + r->size > s)
s = r->base + r->size;
}
*start = s;
*end = 0x100000000ULL;
}
/*
* This function fills in the mvebu_mbus_dram_info_nooverlap data
* structure, by looking at the mvebu_mbus_dram_info data, and
* removing the parts of it that overlap with I/O windows.
*/
static void __init
mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
{
uint64_t mbus_bridge_base, mbus_bridge_end;
int cs_nooverlap = 0;
int i;
mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
struct mbus_dram_window *w;
u64 base, size, end;
w = &mvebu_mbus_dram_info.cs[i];
base = w->base;
size = w->size;
end = base + size;
/*
* The CS is fully enclosed inside the MBus bridge
* area, so ignore it.
*/
if (base >= mbus_bridge_base && end <= mbus_bridge_end)
continue;
/*
* Beginning of CS overlaps with end of MBus, raise CS
* base address, and shrink its size.
*/
if (base >= mbus_bridge_base && end > mbus_bridge_end) {
size -= mbus_bridge_end - base;
base = mbus_bridge_end;
}
/*
* End of CS overlaps with beginning of MBus, shrink
* CS size.
*/
if (base < mbus_bridge_base && end > mbus_bridge_base)
size -= end - mbus_bridge_base;
w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
if (mbus->hw_io_coherency)
w->mbus_attr |= ATTR_HW_COHERENCY;
w->base = base;
w->size = size;
}
mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
}
static void __init static void __init
mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
{ {
...@@ -964,6 +1080,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, ...@@ -964,6 +1080,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
mvebu_mbus_disable_window(mbus, win); mvebu_mbus_disable_window(mbus, win);
mbus->soc->setup_cpu_target(mbus); mbus->soc->setup_cpu_target(mbus);
mvebu_mbus_setup_cpu_target_nooverlap(mbus);
if (is_coherent) if (is_coherent)
writel(UNIT_SYNC_BARRIER_ALL, writel(UNIT_SYNC_BARRIER_ALL,
......
...@@ -502,12 +502,13 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = { ...@@ -502,12 +502,13 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = {
static void __init berlin2_clock_setup(struct device_node *np) static void __init berlin2_clock_setup(struct device_node *np)
{ {
struct device_node *parent_np = of_get_parent(np);
const char *parent_names[9]; const char *parent_names[9];
struct clk *clk; struct clk *clk;
u8 avpll_flags = 0; u8 avpll_flags = 0;
int n; int n;
gbase = of_iomap(np, 0); gbase = of_iomap(parent_np, 0);
if (!gbase) if (!gbase)
return; return;
...@@ -685,7 +686,5 @@ static void __init berlin2_clock_setup(struct device_node *np) ...@@ -685,7 +686,5 @@ static void __init berlin2_clock_setup(struct device_node *np)
bg2_fail: bg2_fail:
iounmap(gbase); iounmap(gbase);
} }
CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-chip-ctrl", CLK_OF_DECLARE(berlin2_clk, "marvell,berlin2-clk",
berlin2_clock_setup);
CLK_OF_DECLARE(berlin2cd_clock, "marvell,berlin2cd-chip-ctrl",
berlin2_clock_setup); berlin2_clock_setup);
...@@ -290,18 +290,19 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = { ...@@ -290,18 +290,19 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = {
static void __init berlin2q_clock_setup(struct device_node *np) static void __init berlin2q_clock_setup(struct device_node *np)
{ {
struct device_node *parent_np = of_get_parent(np);
const char *parent_names[9]; const char *parent_names[9];
struct clk *clk; struct clk *clk;
int n; int n;
gbase = of_iomap(np, 0); gbase = of_iomap(parent_np, 0);
if (!gbase) { if (!gbase) {
pr_err("%s: Unable to map global base\n", np->full_name); pr_err("%s: Unable to map global base\n", np->full_name);
return; return;
} }
/* BG2Q CPU PLL is not part of global registers */ /* BG2Q CPU PLL is not part of global registers */
cpupll_base = of_iomap(np, 1); cpupll_base = of_iomap(parent_np, 1);
if (!cpupll_base) { if (!cpupll_base) {
pr_err("%s: Unable to map cpupll base\n", np->full_name); pr_err("%s: Unable to map cpupll base\n", np->full_name);
iounmap(gbase); iounmap(gbase);
...@@ -384,5 +385,5 @@ static void __init berlin2q_clock_setup(struct device_node *np) ...@@ -384,5 +385,5 @@ static void __init berlin2q_clock_setup(struct device_node *np)
iounmap(cpupll_base); iounmap(cpupll_base);
iounmap(gbase); iounmap(gbase);
} }
CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-chip-ctrl", CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
berlin2q_clock_setup); berlin2q_clock_setup);
...@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o ...@@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_EFI) += efi/
......
This diff is collapsed.
This diff is collapsed.
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __QCOM_SCM_INT_H
#define __QCOM_SCM_INT_H
#define QCOM_SCM_SVC_BOOT 0x1
#define QCOM_SCM_BOOT_ADDR 0x1
#define QCOM_SCM_BOOT_ADDR_MC 0x11
#define QCOM_SCM_FLAG_HLOS 0x01
#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
extern int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
#define QCOM_SCM_CMD_TERMINATE_PC 0x2
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
extern void __qcom_scm_cpu_power_down(u32 flags);
#define QCOM_SCM_SVC_INFO 0x6
#define QCOM_IS_CALL_AVAIL_CMD 0x1
extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id);
#define QCOM_SCM_SVC_HDCP 0x11
#define QCOM_SCM_CMD_HDCP 0x01
extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
u32 *resp);
/* common error codes */
#define QCOM_SCM_ENOMEM -5
#define QCOM_SCM_EOPNOTSUPP -4
#define QCOM_SCM_EINVAL_ADDR -3
#define QCOM_SCM_EINVAL_ARG -2
#define QCOM_SCM_ERROR -1
#define QCOM_SCM_INTERRUPTED 1
#endif
...@@ -219,7 +219,7 @@ config TEGRA_IOMMU_SMMU ...@@ -219,7 +219,7 @@ config TEGRA_IOMMU_SMMU
select IOMMU_API select IOMMU_API
help help
This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
SoCs (Tegra30 up to Tegra124). SoCs (Tegra30 up to Tegra132).
config EXYNOS_IOMMU config EXYNOS_IOMMU
bool "Exynos IOMMU Support" bool "Exynos IOMMU Support"
......
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
*/ */
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/iommu.h> #include <linux/iommu.h>
#include <linux/kernel.h> #include <linux/kernel.h>
...@@ -31,6 +32,8 @@ struct tegra_smmu { ...@@ -31,6 +32,8 @@ struct tegra_smmu {
struct mutex lock; struct mutex lock;
struct list_head list; struct list_head list;
struct dentry *debugfs;
}; };
struct tegra_smmu_as { struct tegra_smmu_as {
...@@ -673,6 +676,103 @@ static void tegra_smmu_ahb_enable(void) ...@@ -673,6 +676,103 @@ static void tegra_smmu_ahb_enable(void)
} }
} }
static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
{
struct tegra_smmu *smmu = s->private;
unsigned int i;
u32 value;
seq_printf(s, "swgroup enabled ASID\n");
seq_printf(s, "------------------------\n");
for (i = 0; i < smmu->soc->num_swgroups; i++) {
const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
const char *status;
unsigned int asid;
value = smmu_readl(smmu, group->reg);
if (value & SMMU_ASID_ENABLE)
status = "yes";
else
status = "no";
asid = value & SMMU_ASID_MASK;
seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
asid);
}
return 0;
}
static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file)
{
return single_open(file, tegra_smmu_swgroups_show, inode->i_private);
}
static const struct file_operations tegra_smmu_swgroups_fops = {
.open = tegra_smmu_swgroups_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int tegra_smmu_clients_show(struct seq_file *s, void *data)
{
struct tegra_smmu *smmu = s->private;
unsigned int i;
u32 value;
seq_printf(s, "client enabled\n");
seq_printf(s, "--------------------\n");
for (i = 0; i < smmu->soc->num_clients; i++) {
const struct tegra_mc_client *client = &smmu->soc->clients[i];
const char *status;
value = smmu_readl(smmu, client->smmu.reg);
if (value & BIT(client->smmu.bit))
status = "yes";
else
status = "no";
seq_printf(s, "%-12s %s\n", client->name, status);
}
return 0;
}
static int tegra_smmu_clients_open(struct inode *inode, struct file *file)
{
return single_open(file, tegra_smmu_clients_show, inode->i_private);
}
static const struct file_operations tegra_smmu_clients_fops = {
.open = tegra_smmu_clients_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
{
smmu->debugfs = debugfs_create_dir("smmu", NULL);
if (!smmu->debugfs)
return;
debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
&tegra_smmu_swgroups_fops);
debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
&tegra_smmu_clients_fops);
}
static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
{
debugfs_remove_recursive(smmu->debugfs);
}
struct tegra_smmu *tegra_smmu_probe(struct device *dev, struct tegra_smmu *tegra_smmu_probe(struct device *dev,
const struct tegra_smmu_soc *soc, const struct tegra_smmu_soc *soc,
struct tegra_mc *mc) struct tegra_mc *mc)
...@@ -743,5 +843,14 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev, ...@@ -743,5 +843,14 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
if (err < 0) if (err < 0)
return ERR_PTR(err); return ERR_PTR(err);
if (IS_ENABLED(CONFIG_DEBUG_FS))
tegra_smmu_debugfs_init(smmu);
return smmu; return smmu;
} }
void tegra_smmu_remove(struct tegra_smmu *smmu)
{
if (IS_ENABLED(CONFIG_DEBUG_FS))
tegra_smmu_debugfs_exit(smmu);
}
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
#include <linux/io.h> #include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
...@@ -66,102 +67,101 @@ static void syscon_led_set(struct led_classdev *led_cdev, ...@@ -66,102 +67,101 @@ static void syscon_led_set(struct led_classdev *led_cdev,
dev_err(sled->cdev.dev, "error updating LED status\n"); dev_err(sled->cdev.dev, "error updating LED status\n");
} }
static int __init syscon_leds_spawn(struct device_node *np, static int syscon_led_probe(struct platform_device *pdev)
struct device *dev,
struct regmap *map)
{ {
struct device_node *child; struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device *parent;
struct regmap *map;
struct syscon_led *sled;
const char *state;
int ret; int ret;
for_each_available_child_of_node(np, child) { parent = dev->parent;
struct syscon_led *sled; if (!parent) {
const char *state; dev_err(dev, "no parent for syscon LED\n");
return -ENODEV;
/* Only check for register-bit-leds */ }
if (of_property_match_string(child, "compatible", map = syscon_node_to_regmap(parent->of_node);
"register-bit-led") < 0) if (!map) {
continue; dev_err(dev, "no regmap for syscon LED parent\n");
return -ENODEV;
sled = devm_kzalloc(dev, sizeof(*sled), GFP_KERNEL); }
if (!sled)
return -ENOMEM; sled = devm_kzalloc(dev, sizeof(*sled), GFP_KERNEL);
if (!sled)
sled->map = map; return -ENOMEM;
if (of_property_read_u32(child, "offset", &sled->offset)) sled->map = map;
return -EINVAL;
if (of_property_read_u32(child, "mask", &sled->mask)) if (of_property_read_u32(np, "offset", &sled->offset))
return -EINVAL; return -EINVAL;
sled->cdev.name = if (of_property_read_u32(np, "mask", &sled->mask))
of_get_property(child, "label", NULL) ? : child->name; return -EINVAL;
sled->cdev.default_trigger = sled->cdev.name =
of_get_property(child, "linux,default-trigger", NULL); of_get_property(np, "label", NULL) ? : np->name;
sled->cdev.default_trigger =
state = of_get_property(child, "default-state", NULL); of_get_property(np, "linux,default-trigger", NULL);
if (state) {
if (!strcmp(state, "keep")) { state = of_get_property(np, "default-state", NULL);
u32 val; if (state) {
if (!strcmp(state, "keep")) {
ret = regmap_read(map, sled->offset, &val); u32 val;
if (ret < 0)
return ret; ret = regmap_read(map, sled->offset, &val);
sled->state = !!(val & sled->mask); if (ret < 0)
} else if (!strcmp(state, "on")) { return ret;
sled->state = true; sled->state = !!(val & sled->mask);
ret = regmap_update_bits(map, sled->offset, } else if (!strcmp(state, "on")) {
sled->mask, sled->state = true;
sled->mask); ret = regmap_update_bits(map, sled->offset,
if (ret < 0) sled->mask,
return ret; sled->mask);
} else { if (ret < 0)
sled->state = false; return ret;
ret = regmap_update_bits(map, sled->offset, } else {
sled->mask, 0); sled->state = false;
if (ret < 0) ret = regmap_update_bits(map, sled->offset,
return ret; sled->mask, 0);
} if (ret < 0)
return ret;
} }
sled->cdev.brightness_set = syscon_led_set; }
sled->cdev.brightness_set = syscon_led_set;
ret = led_classdev_register(dev, &sled->cdev); ret = led_classdev_register(dev, &sled->cdev);
if (ret < 0) if (ret < 0)
return ret; return ret;
platform_set_drvdata(pdev, sled);
dev_info(dev, "registered LED %s\n", sled->cdev.name);
dev_info(dev, "registered LED %s\n", sled->cdev.name);
}
return 0; return 0;
} }
static int __init syscon_leds_init(void) static int syscon_led_remove(struct platform_device *pdev)
{ {
struct device_node *np; struct syscon_led *sled = platform_get_drvdata(pdev);
for_each_of_allnodes(np) {
struct platform_device *pdev;
struct regmap *map;
int ret;
if (!of_device_is_compatible(np, "syscon")) led_classdev_unregister(&sled->cdev);
continue; /* Turn it off */
regmap_update_bits(sled->map, sled->offset, sled->mask, 0);
return 0;
}
map = syscon_node_to_regmap(np); static const struct of_device_id of_syscon_leds_match[] = {
if (IS_ERR(map)) { { .compatible = "register-bit-led", },
pr_err("error getting regmap for syscon LEDs\n"); {},
continue; };
}
/* MODULE_DEVICE_TABLE(of, of_syscon_leds_match);
* If the map is there, the device should be there, we allocate
* memory on the syscon device's behalf here.
*/
pdev = of_find_device_by_node(np);
if (!pdev)
return -ENODEV;
ret = syscon_leds_spawn(np, &pdev->dev, map);
if (ret)
dev_err(&pdev->dev, "could not spawn syscon LEDs\n");
}
return 0; static struct platform_driver syscon_led_driver = {
} .probe = syscon_led_probe,
device_initcall(syscon_leds_init); .remove = syscon_led_remove,
.driver = {
.name = "leds-syscon",
.of_match_table = of_syscon_leds_match,
},
};
module_platform_driver(syscon_led_driver);
...@@ -5,3 +5,13 @@ config TEGRA_MC ...@@ -5,3 +5,13 @@ config TEGRA_MC
help help
This driver supports the Memory Controller (MC) hardware found on This driver supports the Memory Controller (MC) hardware found on
NVIDIA Tegra SoCs. NVIDIA Tegra SoCs.
config TEGRA124_EMC
bool "NVIDIA Tegra124 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_124_SOC
help
This driver is for the External Memory Controller (EMC) found on
Tegra124 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
...@@ -3,5 +3,8 @@ tegra-mc-y := mc.o ...@@ -3,5 +3,8 @@ tegra-mc-y := mc.o
tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
...@@ -13,6 +13,9 @@ ...@@ -13,6 +13,9 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/sort.h>
#include <soc/tegra/fuse.h>
#include "mc.h" #include "mc.h"
...@@ -48,6 +51,9 @@ ...@@ -48,6 +51,9 @@
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
#define MC_EMEM_ARB_MISC0 0xd8 #define MC_EMEM_ARB_MISC0 0xd8
#define MC_EMEM_ADR_CFG 0x54
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
static const struct of_device_id tegra_mc_of_match[] = { static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_3x_SOC #ifdef CONFIG_ARCH_TEGRA_3x_SOC
{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
...@@ -57,6 +63,9 @@ static const struct of_device_id tegra_mc_of_match[] = { ...@@ -57,6 +63,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
#endif #endif
#ifdef CONFIG_ARCH_TEGRA_124_SOC #ifdef CONFIG_ARCH_TEGRA_124_SOC
{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_132_SOC
{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
#endif #endif
{ } { }
}; };
...@@ -91,6 +100,130 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) ...@@ -91,6 +100,130 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
return 0; return 0;
} }
void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
{
unsigned int i;
struct tegra_mc_timing *timing = NULL;
for (i = 0; i < mc->num_timings; i++) {
if (mc->timings[i].rate == rate) {
timing = &mc->timings[i];
break;
}
}
if (!timing) {
dev_err(mc->dev, "no memory timing registered for rate %lu\n",
rate);
return;
}
for (i = 0; i < mc->soc->num_emem_regs; ++i)
mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
}
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
{
u8 dram_count;
dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
dram_count++;
return dram_count;
}
static int load_one_timing(struct tegra_mc *mc,
struct tegra_mc_timing *timing,
struct device_node *node)
{
int err;
u32 tmp;
err = of_property_read_u32(node, "clock-frequency", &tmp);
if (err) {
dev_err(mc->dev,
"timing %s: failed to read rate\n", node->name);
return err;
}
timing->rate = tmp;
timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
sizeof(u32), GFP_KERNEL);
if (!timing->emem_data)
return -ENOMEM;
err = of_property_read_u32_array(node, "nvidia,emem-configuration",
timing->emem_data,
mc->soc->num_emem_regs);
if (err) {
dev_err(mc->dev,
"timing %s: failed to read EMEM configuration\n",
node->name);
return err;
}
return 0;
}
static int load_timings(struct tegra_mc *mc, struct device_node *node)
{
struct device_node *child;
struct tegra_mc_timing *timing;
int child_count = of_get_child_count(node);
int i = 0, err;
mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
GFP_KERNEL);
if (!mc->timings)
return -ENOMEM;
mc->num_timings = child_count;
for_each_child_of_node(node, child) {
timing = &mc->timings[i++];
err = load_one_timing(mc, timing, child);
if (err)
return err;
}
return 0;
}
static int tegra_mc_setup_timings(struct tegra_mc *mc)
{
struct device_node *node;
u32 ram_code, node_ram_code;
int err;
ram_code = tegra_read_ram_code();
mc->num_timings = 0;
for_each_child_of_node(mc->dev->of_node, node) {
err = of_property_read_u32(node, "nvidia,ram-code",
&node_ram_code);
if (err || (node_ram_code != ram_code)) {
of_node_put(node);
continue;
}
err = load_timings(mc, node);
if (err)
return err;
of_node_put(node);
break;
}
if (mc->num_timings == 0)
dev_warn(mc->dev,
"no memory timings for RAM code %u registered\n",
ram_code);
return 0;
}
static const char *const status_names[32] = { static const char *const status_names[32] = {
[ 1] = "External interrupt", [ 1] = "External interrupt",
[ 6] = "EMEM address decode error", [ 6] = "EMEM address decode error",
...@@ -248,6 +381,12 @@ static int tegra_mc_probe(struct platform_device *pdev) ...@@ -248,6 +381,12 @@ static int tegra_mc_probe(struct platform_device *pdev)
return err; return err;
} }
err = tegra_mc_setup_timings(mc);
if (err < 0) {
dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
return err;
}
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
if (IS_ERR(mc->smmu)) { if (IS_ERR(mc->smmu)) {
...@@ -273,8 +412,8 @@ static int tegra_mc_probe(struct platform_device *pdev) ...@@ -273,8 +412,8 @@ static int tegra_mc_probe(struct platform_device *pdev)
value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_ARBITRATION_EMEM | MC_INT_SECURITY_VIOLATION | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
MC_INT_DECERR_EMEM;
mc_writel(mc, value, MC_INTMASK); mc_writel(mc, value, MC_INTMASK);
return 0; return 0;
......
...@@ -37,4 +37,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc; ...@@ -37,4 +37,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc;
extern const struct tegra_mc_soc tegra124_mc_soc; extern const struct tegra_mc_soc tegra124_mc_soc;
#endif #endif
#ifdef CONFIG_ARCH_TEGRA_132_SOC
extern const struct tegra_mc_soc tegra132_mc_soc;
#endif
#endif /* MEMORY_TEGRA_MC_H */ #endif /* MEMORY_TEGRA_MC_H */
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...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
const struct of_device_id of_default_bus_match_table[] = { const struct of_device_id of_default_bus_match_table[] = {
{ .compatible = "simple-bus", }, { .compatible = "simple-bus", },
{ .compatible = "simple-mfd", },
#ifdef CONFIG_ARM_AMBA #ifdef CONFIG_ARM_AMBA
{ .compatible = "arm,amba-bus", }, { .compatible = "arm,amba-bus", },
#endif /* CONFIG_ARM_AMBA */ #endif /* CONFIG_ARM_AMBA */
......
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...@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" ...@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/mediatek/Kconfig" source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig" source "drivers/soc/qcom/Kconfig"
source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/ti/Kconfig" source "drivers/soc/ti/Kconfig"
source "drivers/soc/versatile/Kconfig" source "drivers/soc/versatile/Kconfig"
......
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_TI) += ti/
obj-$(CONFIG_PLAT_VERSATILE) += versatile/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/
...@@ -10,3 +10,10 @@ config QCOM_GSBI ...@@ -10,3 +10,10 @@ config QCOM_GSBI
functions for connecting the underlying serial UART, SPI, and I2C functions for connecting the underlying serial UART, SPI, and I2C
devices to the output pins. devices to the output pins.
config QCOM_PM
bool "Qualcomm Power Management"
depends on ARCH_QCOM && !ARM64
help
QCOM Platform specific power driver to manage cores and L2 low power
modes. It interface with various system drivers to put the cores in
low power modes.
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