Commit 3246fdaa authored by Jacek Anaszewski's avatar Jacek Anaszewski Committed by Mauro Carvalho Chehab

[media] s5p-jpeg: Add support for Exynos3250 SoC

This patch adds support for jpeg codec on Exynos3250 SoC to
the s5p-jpeg driver. Supported raw formats are: YUYV, YVYU, UYVY,
VYUY, RGB565, RGB565X, RGB32, NV12, NV21. The support includes
also scaling and cropping features.
Signed-off-by: default avatarJacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent 1774afe7
......@@ -167,12 +167,13 @@ config VIDEO_SAMSUNG_S5P_G2D
2d graphics accelerator.
config VIDEO_SAMSUNG_S5P_JPEG
tristate "Samsung S5P/Exynos4 JPEG codec driver"
tristate "Samsung S5P/Exynos3250/Exynos4 JPEG codec driver"
depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
---help---
This is a v4l2 driver for Samsung S5P and EXYNOS4 JPEG codec
This is a v4l2 driver for Samsung S5P, EXYNOS3250
and EXYNOS4 JPEG codec
config VIDEO_SAMSUNG_S5P_MFC
tristate "Samsung S5P MFC Video Codec"
......
s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg.o
This diff is collapsed.
......@@ -35,6 +35,8 @@
#define S5P_JPEG_COEF32 0x6e
#define S5P_JPEG_COEF33 0x13
#define EXYNOS3250_IRQ_TIMEOUT 0x10000000
/* a selection of JPEG markers */
#define TEM 0x01
#define SOF0 0xc0
......@@ -49,9 +51,10 @@
#define SJPEG_FMT_FLAG_DEC_CAPTURE (1 << 2)
#define SJPEG_FMT_FLAG_DEC_OUTPUT (1 << 3)
#define SJPEG_FMT_FLAG_S5P (1 << 4)
#define SJPEG_FMT_FLAG_EXYNOS4 (1 << 5)
#define SJPEG_FMT_RGB (1 << 6)
#define SJPEG_FMT_NON_RGB (1 << 7)
#define SJPEG_FMT_FLAG_EXYNOS3250 (1 << 5)
#define SJPEG_FMT_FLAG_EXYNOS4 (1 << 6)
#define SJPEG_FMT_RGB (1 << 7)
#define SJPEG_FMT_NON_RGB (1 << 8)
#define S5P_JPEG_ENCODE 0
#define S5P_JPEG_DECODE 1
......@@ -65,8 +68,9 @@
/* Version numbers */
#define SJPEG_S5P 1
#define SJPEG_EXYNOS4 2
#define SJPEG_S5P 1
#define SJPEG_EXYNOS3250 2
#define SJPEG_EXYNOS4 3
enum exynos4_jpeg_result {
OK_ENC_OR_DEC,
......@@ -95,8 +99,13 @@ enum exynos4_jpeg_img_quality_level {
* @regs: JPEG IP registers mapping
* @irq: JPEG IP irq
* @clk: JPEG IP clock
* @sclk: Exynos3250 JPEG IP special clock
* @dev: JPEG IP struct device
* @alloc_ctx: videobuf2 memory allocator's context
* @variant: driver variant to be used
* @irq_status interrupt flags set during single encode/decode
operation
*/
struct s5p_jpeg {
struct mutex lock;
......@@ -111,9 +120,11 @@ struct s5p_jpeg {
unsigned int irq;
enum exynos4_jpeg_result irq_ret;
struct clk *clk;
struct clk *sclk;
struct device *dev;
void *alloc_ctx;
struct s5p_jpeg_variant *variant;
u32 irq_status;
};
struct s5p_jpeg_variant {
......@@ -164,9 +175,15 @@ struct s5p_jpeg_q_data {
* @jpeg: JPEG IP device for this context
* @mode: compression (encode) operation or decompression (decode)
* @compr_quality: destination image quality in compression (encode) mode
* @restart_interval: JPEG restart interval for JPEG encoding
* @subsampling: subsampling of a raw format or a JPEG
* @out_q: source (output) queue information
* @cap_fmt: destination (capture) queue queue information
* @cap_q: destination (capture) queue queue information
* @scale_factor: scale factor for JPEG decoding
* @crop_rect: a rectangle representing crop area of the output buffer
* @fh: V4L2 file handle
* @hdr_parsed: set if header has been parsed during decompression
* @crop_altered: set if crop rectangle has been altered by the user space
* @ctrl_handler: controls handler
*/
struct s5p_jpeg_ctx {
......@@ -177,8 +194,11 @@ struct s5p_jpeg_ctx {
unsigned short subsampling;
struct s5p_jpeg_q_data out_q;
struct s5p_jpeg_q_data cap_q;
unsigned int scale_factor;
struct v4l2_rect crop_rect;
struct v4l2_fh fh;
bool hdr_parsed;
bool crop_altered;
struct v4l2_ctrl_handler ctrl_handler;
};
......
This diff is collapsed.
/* linux/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.h
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef JPEG_HW_EXYNOS3250_H_
#define JPEG_HW_EXYNOS3250_H_
#include <linux/io.h>
#include <linux/videodev2.h>
#include "jpeg-regs.h"
void exynos3250_jpeg_reset(void __iomem *regs);
void exynos3250_jpeg_poweron(void __iomem *regs);
void exynos3250_jpeg_set_dma_num(void __iomem *regs);
void exynos3250_jpeg_clk_set(void __iomem *base);
void exynos3250_jpeg_input_raw_fmt(void __iomem *regs, unsigned int fmt);
void exynos3250_jpeg_output_raw_fmt(void __iomem *regs, unsigned int fmt);
void exynos3250_jpeg_set_y16(void __iomem *regs, bool y16);
void exynos3250_jpeg_proc_mode(void __iomem *regs, unsigned int mode);
void exynos3250_jpeg_subsampling_mode(void __iomem *regs, unsigned int mode);
unsigned int exynos3250_jpeg_get_subsampling_mode(void __iomem *regs);
void exynos3250_jpeg_dri(void __iomem *regs, unsigned int dri);
void exynos3250_jpeg_qtbl(void __iomem *regs, unsigned int t, unsigned int n);
void exynos3250_jpeg_htbl_ac(void __iomem *regs, unsigned int t);
void exynos3250_jpeg_htbl_dc(void __iomem *regs, unsigned int t);
void exynos3250_jpeg_set_y(void __iomem *regs, unsigned int y);
void exynos3250_jpeg_set_x(void __iomem *regs, unsigned int x);
void exynos3250_jpeg_interrupts_enable(void __iomem *regs);
void exynos3250_jpeg_enc_stream_bound(void __iomem *regs, unsigned int size);
void exynos3250_jpeg_outform_raw(void __iomem *regs, unsigned long format);
void exynos3250_jpeg_jpgadr(void __iomem *regs, unsigned int addr);
void exynos3250_jpeg_imgadr(void __iomem *regs, struct s5p_jpeg_addr *img_addr);
void exynos3250_jpeg_stride(void __iomem *regs, unsigned int img_fmt,
unsigned int width);
void exynos3250_jpeg_offset(void __iomem *regs, unsigned int x_offset,
unsigned int y_offset);
void exynos3250_jpeg_coef(void __iomem *base, unsigned int mode);
void exynos3250_jpeg_start(void __iomem *regs);
void exynos3250_jpeg_rstart(void __iomem *regs);
unsigned int exynos3250_jpeg_get_int_status(void __iomem *regs);
void exynos3250_jpeg_clear_int_status(void __iomem *regs,
unsigned int value);
unsigned int exynos3250_jpeg_operating(void __iomem *regs);
unsigned int exynos3250_jpeg_compressed_size(void __iomem *regs);
void exynos3250_jpeg_dec_stream_size(void __iomem *regs, unsigned int size);
void exynos3250_jpeg_dec_scaling_ratio(void __iomem *regs, unsigned int sratio);
void exynos3250_jpeg_set_timer(void __iomem *regs, unsigned int time_value);
unsigned int exynos3250_jpeg_get_timer_status(void __iomem *regs);
void exynos3250_jpeg_set_timer_status(void __iomem *regs);
void exynos3250_jpeg_clear_timer_status(void __iomem *regs);
#endif /* JPEG_HW_EXYNOS3250_H_ */
......@@ -2,7 +2,7 @@
*
* Register definition file for Samsung JPEG codec driver
*
* Copyright (c) 2011-2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Author: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
......@@ -373,5 +373,250 @@
/* JPEG AC chrominance (values) Huffman table register */
#define EXYNOS4_HUFF_TBL_HACCV 0x310
/* Register and bit definitions for Exynos 3250 */
/* JPEG mode register */
#define EXYNOS3250_JPGMOD 0x00
#define EXYNOS3250_PROC_MODE_MASK (0x1 << 3)
#define EXYNOS3250_PROC_MODE_DECOMPR (0x1 << 3)
#define EXYNOS3250_PROC_MODE_COMPR (0x0 << 3)
#define EXYNOS3250_SUBSAMPLING_MODE_MASK (0x7 << 0)
#define EXYNOS3250_SUBSAMPLING_MODE_444 (0x0 << 0)
#define EXYNOS3250_SUBSAMPLING_MODE_422 (0x1 << 0)
#define EXYNOS3250_SUBSAMPLING_MODE_420 (0x2 << 0)
#define EXYNOS3250_SUBSAMPLING_MODE_411 (0x6 << 0)
#define EXYNOS3250_SUBSAMPLING_MODE_GRAY (0x3 << 0)
/* JPEG operation status register */
#define EXYNOS3250_JPGOPR 0x04
#define EXYNOS3250_JPGOPR_MASK 0x01
/* Quantization and Huffman tables register */
#define EXYNOS3250_QHTBL 0x08
#define EXYNOS3250_QT_NUM_SHIFT(t) ((((t) - 1) << 1) + 8)
#define EXYNOS3250_QT_NUM_MASK(t) (0x3 << EXYNOS3250_QT_NUM_SHIFT(t))
/* Huffman tables */
#define EXYNOS3250_HT_NUM_AC_SHIFT(t) (((t) << 1) - 1)
#define EXYNOS3250_HT_NUM_AC_MASK(t) (0x1 << EXYNOS3250_HT_NUM_AC_SHIFT(t))
#define EXYNOS3250_HT_NUM_DC_SHIFT(t) (((t) - 1) << 1)
#define EXYNOS3250_HT_NUM_DC_MASK(t) (0x1 << EXYNOS3250_HT_NUM_DC_SHIFT(t))
/* JPEG restart interval register */
#define EXYNOS3250_JPGDRI 0x0c
#define EXYNOS3250_JPGDRI_MASK 0xffff
/* JPEG vertical resolution register */
#define EXYNOS3250_JPGY 0x10
#define EXYNOS3250_JPGY_MASK 0xffff
/* JPEG horizontal resolution register */
#define EXYNOS3250_JPGX 0x14
#define EXYNOS3250_JPGX_MASK 0xffff
/* JPEG byte count register */
#define EXYNOS3250_JPGCNT 0x18
#define EXYNOS3250_JPGCNT_MASK 0xffffff
/* JPEG interrupt mask register */
#define EXYNOS3250_JPGINTSE 0x1c
#define EXYNOS3250_JPEG_DONE_EN (1 << 11)
#define EXYNOS3250_WDMA_DONE_EN (1 << 10)
#define EXYNOS3250_RDMA_DONE_EN (1 << 9)
#define EXYNOS3250_ENC_STREAM_INT_EN (1 << 8)
#define EXYNOS3250_CORE_DONE_EN (1 << 5)
#define EXYNOS3250_ERR_INT_EN (1 << 4)
#define EXYNOS3250_HEAD_INT_EN (1 << 3)
/* JPEG interrupt status register */
#define EXYNOS3250_JPGINTST 0x20
#define EXYNOS3250_JPEG_DONE (1 << 11)
#define EXYNOS3250_WDMA_DONE (1 << 10)
#define EXYNOS3250_RDMA_DONE (1 << 9)
#define EXYNOS3250_ENC_STREAM_STAT (1 << 8)
#define EXYNOS3250_RESULT_STAT (1 << 5)
#define EXYNOS3250_STREAM_STAT (1 << 4)
#define EXYNOS3250_HEADER_STAT (1 << 3)
/*
* Base address of the luma component DMA buffer
* of the raw input or output image.
*/
#define EXYNOS3250_LUMA_BASE 0x100
#define EXYNOS3250_SRC_TILE_EN_MASK 0x100
/* Stride of source or destination luma raw image buffer */
#define EXYNOS3250_LUMA_STRIDE 0x104
/* Horizontal/vertical offset of active region in luma raw image buffer */
#define EXYNOS3250_LUMA_XY_OFFSET 0x108
#define EXYNOS3250_LUMA_YY_OFFSET_SHIFT 18
#define EXYNOS3250_LUMA_YY_OFFSET_MASK (0x1fff << EXYNOS3250_LUMA_YY_OFFSET_SHIFT)
#define EXYNOS3250_LUMA_YX_OFFSET_SHIFT 2
#define EXYNOS3250_LUMA_YX_OFFSET_MASK (0x1fff << EXYNOS3250_LUMA_YX_OFFSET_SHIFT)
/*
* Base address of the chroma(Cb) component DMA buffer
* of the raw input or output image.
*/
#define EXYNOS3250_CHROMA_BASE 0x10c
/* Stride of source or destination chroma(Cb) raw image buffer */
#define EXYNOS3250_CHROMA_STRIDE 0x110
/* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */
#define EXYNOS3250_CHROMA_XY_OFFSET 0x114
#define EXYNOS3250_CHROMA_YY_OFFSET_SHIFT 18
#define EXYNOS3250_CHROMA_YY_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_YY_OFFSET_SHIFT)
#define EXYNOS3250_CHROMA_YX_OFFSET_SHIFT 2
#define EXYNOS3250_CHROMA_YX_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_YX_OFFSET_SHIFT)
/*
* Base address of the chroma(Cr) component DMA buffer
* of the raw input or output image.
*/
#define EXYNOS3250_CHROMA_CR_BASE 0x118
/* Stride of source or destination chroma(Cr) raw image buffer */
#define EXYNOS3250_CHROMA_CR_STRIDE 0x11c
/* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */
#define EXYNOS3250_CHROMA_CR_XY_OFFSET 0x120
#define EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT 18
#define EXYNOS3250_CHROMA_CR_YY_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT)
#define EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT 2
#define EXYNOS3250_CHROMA_CR_YX_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT)
/* Raw image data r/w address register */
#define EXYNOS3250_JPG_IMGADR 0x50
/* Source or destination JPEG file DMA buffer address */
#define EXYNOS3250_JPG_JPGADR 0x124
/* Coefficients for RGB-to-YCbCr converter register */
#define EXYNOS3250_JPG_COEF(n) (0x128 + (((n) - 1) << 2))
#define EXYNOS3250_COEF_SHIFT(j) ((3 - (j)) << 3)
#define EXYNOS3250_COEF_MASK(j) (0xff << EXYNOS3250_COEF_SHIFT(j))
/* Raw input format setting */
#define EXYNOS3250_JPGCMOD 0x134
#define EXYNOS3250_SRC_TILE_EN (0x1 << 10)
#define EXYNOS3250_SRC_NV_MASK (0x1 << 9)
#define EXYNOS3250_SRC_NV12 (0x0 << 9)
#define EXYNOS3250_SRC_NV21 (0x1 << 9)
#define EXYNOS3250_SRC_BIG_ENDIAN_MASK (0x1 << 8)
#define EXYNOS3250_SRC_BIG_ENDIAN (0x1 << 8)
#define EXYNOS3250_MODE_SEL_MASK (0x7 << 5)
#define EXYNOS3250_MODE_SEL_420_2P (0x0 << 5)
#define EXYNOS3250_MODE_SEL_422_1P_LUM_CHR (0x1 << 5)
#define EXYNOS3250_MODE_SEL_RGB565 (0x2 << 5)
#define EXYNOS3250_MODE_SEL_422_1P_CHR_LUM (0x3 << 5)
#define EXYNOS3250_MODE_SEL_ARGB8888 (0x4 << 5)
#define EXYNOS3250_MODE_SEL_420_3P (0x5 << 5)
#define EXYNOS3250_SRC_SWAP_RGB (0x1 << 3)
#define EXYNOS3250_SRC_SWAP_UV (0x1 << 2)
#define EXYNOS3250_MODE_Y16_MASK (0x1 << 1)
#define EXYNOS3250_MODE_Y16 (0x1 << 1)
#define EXYNOS3250_HALF_EN_MASK (0x1 << 0)
#define EXYNOS3250_HALF_EN (0x1 << 0)
/* Power on/off and clock down control */
#define EXYNOS3250_JPGCLKCON 0x138
#define EXYNOS3250_CLK_DOWN_READY (0x1 << 1)
#define EXYNOS3250_POWER_ON (0x1 << 0)
/* Start compression or decompression */
#define EXYNOS3250_JSTART 0x13c
/* Restart decompression after header analysis */
#define EXYNOS3250_JRSTART 0x140
/* JPEG SW reset register */
#define EXYNOS3250_SW_RESET 0x144
/* JPEG timer setting register */
#define EXYNOS3250_TIMER_SE 0x148
#define EXYNOS3250_TIMER_INT_EN_SHIFT 31
#define EXYNOS3250_TIMER_INT_EN (1 << EXYNOS3250_TIMER_INT_EN_SHIFT)
#define EXYNOS3250_TIMER_INIT_MASK 0x7fffffff
/* JPEG timer status register */
#define EXYNOS3250_TIMER_ST 0x14c
#define EXYNOS3250_TIMER_INT_STAT_SHIFT 31
#define EXYNOS3250_TIMER_INT_STAT (1 << EXYNOS3250_TIMER_INT_STAT_SHIFT)
#define EXYNOS3250_TIMER_CNT_SHIFT 0
#define EXYNOS3250_TIMER_CNT_MASK 0x7fffffff
/* Command status register */
#define EXYNOS3250_COMSTAT 0x150
#define EXYNOS3250_CUR_PROC_MODE (0x1 << 1)
#define EXYNOS3250_CUR_COM_MODE (0x1 << 0)
/* JPEG decompression output format register */
#define EXYNOS3250_OUTFORM 0x154
#define EXYNOS3250_OUT_ALPHA_MASK (0xff << 24)
#define EXYNOS3250_OUT_TILE_EN (0x1 << 10)
#define EXYNOS3250_OUT_NV_MASK (0x1 << 9)
#define EXYNOS3250_OUT_NV12 (0x0 << 9)
#define EXYNOS3250_OUT_NV21 (0x1 << 9)
#define EXYNOS3250_OUT_BIG_ENDIAN_MASK (0x1 << 8)
#define EXYNOS3250_OUT_BIG_ENDIAN (0x1 << 8)
#define EXYNOS3250_OUT_SWAP_RGB (0x1 << 7)
#define EXYNOS3250_OUT_SWAP_UV (0x1 << 6)
#define EXYNOS3250_OUT_FMT_MASK (0x7 << 0)
#define EXYNOS3250_OUT_FMT_420_2P (0x0 << 0)
#define EXYNOS3250_OUT_FMT_422_1P_LUM_CHR (0x1 << 0)
#define EXYNOS3250_OUT_FMT_422_1P_CHR_LUM (0x3 << 0)
#define EXYNOS3250_OUT_FMT_420_3P (0x4 << 0)
#define EXYNOS3250_OUT_FMT_RGB565 (0x5 << 0)
#define EXYNOS3250_OUT_FMT_ARGB8888 (0x6 << 0)
/* Input JPEG stream byte size for decompression */
#define EXYNOS3250_DEC_STREAM_SIZE 0x158
#define EXYNOS3250_DEC_STREAM_MASK 0x1fffffff
/* The upper bound of the byte size of output compressed stream */
#define EXYNOS3250_ENC_STREAM_BOUND 0x15c
#define EXYNOS3250_ENC_STREAM_BOUND_MASK 0xffffc0
/* Scale-down ratio when decoding */
#define EXYNOS3250_DEC_SCALING_RATIO 0x160
#define EXYNOS3250_DEC_SCALE_FACTOR_MASK 0x3
#define EXYNOS3250_DEC_SCALE_FACTOR_8_8 0x0
#define EXYNOS3250_DEC_SCALE_FACTOR_4_8 0x1
#define EXYNOS3250_DEC_SCALE_FACTOR_2_8 0x2
#define EXYNOS3250_DEC_SCALE_FACTOR_1_8 0x3
/* Error check */
#define EXYNOS3250_CRC_RESULT 0x164
/* RDMA and WDMA operation status register */
#define EXYNOS3250_DMA_OPER_STATUS 0x168
#define EXYNOS3250_WDMA_OPER_STATUS (0x1 << 1)
#define EXYNOS3250_RDMA_OPER_STATUS (0x1 << 0)
/* DMA issue gathering number and issue number settings */
#define EXYNOS3250_DMA_ISSUE_NUM 0x16c
#define EXYNOS3250_WDMA_ISSUE_NUM_SHIFT 16
#define EXYNOS3250_WDMA_ISSUE_NUM_MASK (0x7 << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT)
#define EXYNOS3250_RDMA_ISSUE_NUM_SHIFT 8
#define EXYNOS3250_RDMA_ISSUE_NUM_MASK (0x7 << EXYNOS3250_RDMA_ISSUE_NUM_SHIFT)
#define EXYNOS3250_ISSUE_GATHER_NUM_SHIFT 0
#define EXYNOS3250_ISSUE_GATHER_NUM_MASK (0x7 << EXYNOS3250_ISSUE_GATHER_NUM_SHIFT)
#define EXYNOS3250_DMA_MO_COUNT 0x7
/* Version register */
#define EXYNOS3250_VERSION 0x1fc
/* RGB <-> YUV conversion coefficients */
#define EXYNOS3250_JPEG_ENC_COEF1 0x01352e1e
#define EXYNOS3250_JPEG_ENC_COEF2 0x00b0ae83
#define EXYNOS3250_JPEG_ENC_COEF3 0x020cdc13
#define EXYNOS3250_JPEG_DEC_COEF1 0x04a80199
#define EXYNOS3250_JPEG_DEC_COEF2 0x04a9a064
#define EXYNOS3250_JPEG_DEC_COEF3 0x04a80102
#endif /* JPEG_REGS_H_ */
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