Commit 34e3205e authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gmc8: remove duplicate wait_for_idle functions

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5a3f25db
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
static int gmc_v8_0_wait_for_idle(void *handle);
MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
...@@ -147,35 +148,6 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -147,35 +148,6 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
} }
} }
/**
* gmc8_mc_wait_for_idle - wait for MC idle callback.
*
* @adev: amdgpu_device pointer
*
* Wait for the MC (memory controller) to be idle.
* (evergreen+).
* Returns 0 if the MC is idle, -1 if not.
*/
static int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
{
unsigned i;
u32 tmp;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
SRBM_STATUS__MCB_BUSY_MASK |
SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
SRBM_STATUS__MCC_BUSY_MASK |
SRBM_STATUS__MCD_BUSY_MASK |
SRBM_STATUS__VMC1_BUSY_MASK);
if (!tmp)
return 0;
udelay(1);
}
return -1;
}
static void gmc_v8_0_mc_stop(struct amdgpu_device *adev, static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
struct amdgpu_mode_mc_save *save) struct amdgpu_mode_mc_save *save)
{ {
...@@ -184,7 +156,7 @@ static void gmc_v8_0_mc_stop(struct amdgpu_device *adev, ...@@ -184,7 +156,7 @@ static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
if (adev->mode_info.num_crtc) if (adev->mode_info.num_crtc)
amdgpu_display_stop_mc_access(adev, save); amdgpu_display_stop_mc_access(adev, save);
gmc_v8_0_mc_wait_for_idle(adev); gmc_v8_0_wait_for_idle(adev);
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
...@@ -393,7 +365,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) ...@@ -393,7 +365,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
amdgpu_display_set_vga_render_state(adev, false); amdgpu_display_set_vga_render_state(adev, false);
gmc_v8_0_mc_stop(adev, &save); gmc_v8_0_mc_stop(adev, &save);
if (gmc_v8_0_mc_wait_for_idle(adev)) { if (gmc_v8_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n"); dev_warn(adev->dev, "Wait for MC idle timedout !\n");
} }
/* Update configuration */ /* Update configuration */
...@@ -413,7 +385,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) ...@@ -413,7 +385,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
WREG32(mmMC_VM_AGP_BASE, 0); WREG32(mmMC_VM_AGP_BASE, 0);
WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
if (gmc_v8_0_mc_wait_for_idle(adev)) { if (gmc_v8_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for MC idle timedout !\n"); dev_warn(adev->dev, "Wait for MC idle timedout !\n");
} }
gmc_v8_0_mc_resume(adev, &save); gmc_v8_0_mc_resume(adev, &save);
...@@ -1140,7 +1112,7 @@ static int gmc_v8_0_soft_reset(void *handle) ...@@ -1140,7 +1112,7 @@ static int gmc_v8_0_soft_reset(void *handle)
if (srbm_soft_reset) { if (srbm_soft_reset) {
gmc_v8_0_mc_stop(adev, &save); gmc_v8_0_mc_stop(adev, &save);
if (gmc_v8_0_wait_for_idle(adev)) { if (gmc_v8_0_wait_for_idle((void *)adev)) {
dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
} }
......
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