Commit 37aa8aa6 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mark Brown

spi: dw: Add 'mfld' suffix to Intel Medfield related routines

In order to prepare driver for the extension to support newer hardware,
add 'mfld' suffix to some related functions.

While here, move DMA parameters assignment under existing #ifdef
CONFIG_SPI_DW_MID_DMA.

There is no functional change intended.
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200506153025.21441-6-andriy.shevchenko@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent e7940952
...@@ -34,7 +34,7 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param) ...@@ -34,7 +34,7 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
return true; return true;
} }
static int mid_spi_dma_init(struct dw_spi *dws) static int mid_spi_dma_init_mfld(struct dw_spi *dws)
{ {
struct pci_dev *dma_dev; struct pci_dev *dma_dev;
struct dw_dma_slave *tx = dws->dma_tx; struct dw_dma_slave *tx = dws->dma_tx;
...@@ -276,14 +276,23 @@ static void mid_spi_dma_stop(struct dw_spi *dws) ...@@ -276,14 +276,23 @@ static void mid_spi_dma_stop(struct dw_spi *dws)
} }
} }
static const struct dw_spi_dma_ops mid_dma_ops = { static const struct dw_spi_dma_ops mfld_dma_ops = {
.dma_init = mid_spi_dma_init, .dma_init = mid_spi_dma_init_mfld,
.dma_exit = mid_spi_dma_exit, .dma_exit = mid_spi_dma_exit,
.dma_setup = mid_spi_dma_setup, .dma_setup = mid_spi_dma_setup,
.can_dma = mid_spi_can_dma, .can_dma = mid_spi_can_dma,
.dma_transfer = mid_spi_dma_transfer, .dma_transfer = mid_spi_dma_transfer,
.dma_stop = mid_spi_dma_stop, .dma_stop = mid_spi_dma_stop,
}; };
static void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws)
{
dws->dma_tx = &mid_dma_tx;
dws->dma_rx = &mid_dma_rx;
dws->dma_ops = &mfld_dma_ops;
}
#else /* CONFIG_SPI_DW_MID_DMA */
static inline void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws) {}
#endif #endif
/* Some specific info for SPI0 controller on Intel MID */ /* Some specific info for SPI0 controller on Intel MID */
...@@ -297,7 +306,7 @@ static const struct dw_spi_dma_ops mid_dma_ops = { ...@@ -297,7 +306,7 @@ static const struct dw_spi_dma_ops mid_dma_ops = {
#define CLK_SPI_CDIV_MASK 0x00000e00 #define CLK_SPI_CDIV_MASK 0x00000e00
#define CLK_SPI_DISABLE_OFFSET 8 #define CLK_SPI_DISABLE_OFFSET 8
int dw_spi_mid_init(struct dw_spi *dws) int dw_spi_mid_init_mfld(struct dw_spi *dws)
{ {
void __iomem *clk_reg; void __iomem *clk_reg;
u32 clk_cdiv; u32 clk_cdiv;
...@@ -314,14 +323,9 @@ int dw_spi_mid_init(struct dw_spi *dws) ...@@ -314,14 +323,9 @@ int dw_spi_mid_init(struct dw_spi *dws)
iounmap(clk_reg); iounmap(clk_reg);
#ifdef CONFIG_SPI_DW_MID_DMA
dws->dma_tx = &mid_dma_tx;
dws->dma_rx = &mid_dma_rx;
dws->dma_ops = &mid_dma_ops;
#endif
/* Register hook to configure CTRLR0 */ /* Register hook to configure CTRLR0 */
dws->update_cr0 = dw_spi_update_cr0; dws->update_cr0 = dw_spi_update_cr0;
dw_spi_mid_setup_dma_mfld(dws);
return 0; return 0;
} }
...@@ -23,13 +23,13 @@ struct spi_pci_desc { ...@@ -23,13 +23,13 @@ struct spi_pci_desc {
}; };
static struct spi_pci_desc spi_pci_mid_desc_1 = { static struct spi_pci_desc spi_pci_mid_desc_1 = {
.setup = dw_spi_mid_init, .setup = dw_spi_mid_init_mfld,
.num_cs = 5, .num_cs = 5,
.bus_num = 0, .bus_num = 0,
}; };
static struct spi_pci_desc spi_pci_mid_desc_2 = { static struct spi_pci_desc spi_pci_mid_desc_2 = {
.setup = dw_spi_mid_init, .setup = dw_spi_mid_init_mfld,
.num_cs = 2, .num_cs = 2,
.bus_num = 1, .bus_num = 1,
}; };
......
...@@ -260,5 +260,6 @@ extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, ...@@ -260,5 +260,6 @@ extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
struct spi_transfer *transfer); struct spi_transfer *transfer);
/* platform related setup */ /* platform related setup */
extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ extern int dw_spi_mid_init_mfld(struct dw_spi *dws);
#endif /* DW_SPI_HEADER_H */ #endif /* DW_SPI_HEADER_H */
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