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Commit 38d2620e authored by David Miller's avatar David Miller Committed by Paul Mundt
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svga: Make svga_set_timings() take an iomem regbase pointer. 

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 55db0923
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Showing with 21 additions and 20 deletions
drivers/video/arkfb.c
View file @ 38d2620e
...@@ -781,7 +781,7 @@ static int arkfb_set_par(struct fb_info *info) ...@@ -781,7 +781,7 @@ static int arkfb_set_par(struct fb_info *info)
} }
ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul); ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv, svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
(info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
hmul, info->node); hmul, info->node);
......
drivers/video/s3fb.c
View file @ 38d2620e
...@@ -712,7 +712,7 @@ static int s3fb_set_par(struct fb_info *info) ...@@ -712,7 +712,7 @@ static int s3fb_set_par(struct fb_info *info)
} }
s3_set_pixclock(info, info->var.pixclock); s3_set_pixclock(info, info->var.pixclock);
svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1, svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
(info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
hmul, info->node); hmul, info->node);
......
drivers/video/svgalib.c
View file @ 38d2620e
...@@ -507,8 +507,9 @@ int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screenin ...@@ -507,8 +507,9 @@ int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screenin
} }
/* Set CRT timing registers */ /* Set CRT timing registers */
void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm,
u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node) struct fb_var_screeninfo *var,
u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
{ {
u8 regval; u8 regval;
u32 value; u32 value;
...@@ -516,66 +517,66 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf ...@@ -516,66 +517,66 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf
value = var->xres + var->left_margin + var->right_margin + var->hsync_len; value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
value = (value * hmul) / hdiv; value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal total : %d\n", node, value); pr_debug("fb%d: horizontal total : %d\n", node, value);
svga_wcrt_multi(NULL, tm->h_total_regs, (value / 8) - 5); svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5);
value = var->xres; value = var->xres;
value = (value * hmul) / hdiv; value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal display : %d\n", node, value); pr_debug("fb%d: horizontal display : %d\n", node, value);
svga_wcrt_multi(NULL, tm->h_display_regs, (value / 8) - 1); svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1);
value = var->xres; value = var->xres;
value = (value * hmul) / hdiv; value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal blank start: %d\n", node, value); pr_debug("fb%d: horizontal blank start: %d\n", node, value);
svga_wcrt_multi(NULL, tm->h_blank_start_regs, (value / 8) - 1 + hborder); svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder);
value = var->xres + var->left_margin + var->right_margin + var->hsync_len; value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
value = (value * hmul) / hdiv; value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal blank end : %d\n", node, value); pr_debug("fb%d: horizontal blank end : %d\n", node, value);
svga_wcrt_multi(NULL, tm->h_blank_end_regs, (value / 8) - 1 - hborder); svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder);
value = var->xres + var->right_margin; value = var->xres + var->right_margin;
value = (value * hmul) / hdiv; value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal sync start : %d\n", node, value); pr_debug("fb%d: horizontal sync start : %d\n", node, value);
svga_wcrt_multi(NULL, tm->h_sync_start_regs, (value / 8)); svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8));
value = var->xres + var->right_margin + var->hsync_len; value = var->xres + var->right_margin + var->hsync_len;
value = (value * hmul) / hdiv; value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal sync end : %d\n", node, value); pr_debug("fb%d: horizontal sync end : %d\n", node, value);
svga_wcrt_multi(NULL, tm->h_sync_end_regs, (value / 8)); svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8));
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
value = (value * vmul) / vdiv; value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical total : %d\n", node, value); pr_debug("fb%d: vertical total : %d\n", node, value);
svga_wcrt_multi(NULL, tm->v_total_regs, value - 2); svga_wcrt_multi(regbase, tm->v_total_regs, value - 2);
value = var->yres; value = var->yres;
value = (value * vmul) / vdiv; value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical display : %d\n", node, value); pr_debug("fb%d: vertical display : %d\n", node, value);
svga_wcrt_multi(NULL, tm->v_display_regs, value - 1); svga_wcrt_multi(regbase, tm->v_display_regs, value - 1);
value = var->yres; value = var->yres;
value = (value * vmul) / vdiv; value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical blank start : %d\n", node, value); pr_debug("fb%d: vertical blank start : %d\n", node, value);
svga_wcrt_multi(NULL, tm->v_blank_start_regs, value); svga_wcrt_multi(regbase, tm->v_blank_start_regs, value);
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len; value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
value = (value * vmul) / vdiv; value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical blank end : %d\n", node, value); pr_debug("fb%d: vertical blank end : %d\n", node, value);
svga_wcrt_multi(NULL, tm->v_blank_end_regs, value - 2); svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2);
value = var->yres + var->lower_margin; value = var->yres + var->lower_margin;
value = (value * vmul) / vdiv; value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical sync start : %d\n", node, value); pr_debug("fb%d: vertical sync start : %d\n", node, value);
svga_wcrt_multi(NULL, tm->v_sync_start_regs, value); svga_wcrt_multi(regbase, tm->v_sync_start_regs, value);
value = var->yres + var->lower_margin + var->vsync_len; value = var->yres + var->lower_margin + var->vsync_len;
value = (value * vmul) / vdiv; value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical sync end : %d\n", node, value); pr_debug("fb%d: vertical sync end : %d\n", node, value);
svga_wcrt_multi(NULL, tm->v_sync_end_regs, value); svga_wcrt_multi(regbase, tm->v_sync_end_regs, value);
/* Set horizontal and vertical sync pulse polarity in misc register */ /* Set horizontal and vertical sync pulse polarity in misc register */
regval = vga_r(NULL, VGA_MIS_R); regval = vga_r(regbase, VGA_MIS_R);
if (var->sync & FB_SYNC_HOR_HIGH_ACT) { if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
pr_debug("fb%d: positive horizontal sync\n", node); pr_debug("fb%d: positive horizontal sync\n", node);
regval = regval & ~0x80; regval = regval & ~0x80;
...@@ -590,7 +591,7 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf ...@@ -590,7 +591,7 @@ void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninf
pr_debug("fb%d: negative vertical sync\n\n", node); pr_debug("fb%d: negative vertical sync\n\n", node);
regval = regval | 0x40; regval = regval | 0x40;
} }
vga_w(NULL, VGA_MIS_W, regval); vga_w(regbase, VGA_MIS_W, regval);
} }
......
drivers/video/vt8623fb.c
View file @ 38d2620e
...@@ -505,7 +505,7 @@ static int vt8623fb_set_par(struct fb_info *info) ...@@ -505,7 +505,7 @@ static int vt8623fb_set_par(struct fb_info *info)
} }
vt8623_set_pixclock(info, info->var.pixclock); vt8623_set_pixclock(info, info->var.pixclock);
svga_set_timings(&vt8623_timing_regs, &(info->var), 1, 1, svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1, (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1,
1, info->node); 1, info->node);
......
include/linux/svga.h
View file @ 38d2620e
...@@ -116,7 +116,7 @@ void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps, ...@@ -116,7 +116,7 @@ void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps,
int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node); int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node);
int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node); int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node);
void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node); void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node);
int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix); int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix);
......
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