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Commit 38f56f33 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC device tree updates (part 2) from Arnd Bergmann:
 "These are mostly new device tree bindings for existing drivers, as
  well as changes to the device tree source files to add support for
  those devices, and a couple of new boards, most notably Samsung's
  Exynos5 based Chromebook.

  The changes depend on earlier platform specific updates and touch the
  usual platforms: omap, exynos, tegra, mxs, mvebu and davinci."

* tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
  ARM: exynos: dts: cros5250: add EC device
  ARM: dts: Add sbs-battery for exynos5250-snow
  ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
  ARM: dts: add mshc controller node for Exynos4x12 SoCs
  ARM: dts: Add chip-id controller node on Exynos4/5 SoC
  ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
  ARM: davinci: da850-evm: add SPI flash support
  ARM: davinci: da850: override SPI DT node device name
  ARM: davinci: da850: add SPI1 DT node
  spi/davinci: add DT binding documentation
  spi/davinci: no wildcards in DT compatible property
  ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
  ARM: dts: mvebu: introduce internal-regs node
  ARM: dts: mvebu: Convert all the mvebu files to use the range property
  ARM: dts: mvebu: move all peripherals inside soc
  ARM: dts: mvebu: fix cpus section indentation
  ARM: davinci: da850: add EHRPWM & ECAP DT node
  ARM/dts: OMAP3: fix pinctrl-single configuration
  ARM: dts: Add OMAP3430 SDP NOR flash memory binding
  ARM: dts: Add NOR flash bindings for OMAP2420 H4
  ...
parents fcba9145 4183bef2
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Documentation/devicetree/bindings/arm/omap/l3-noc.txt
View file @ 38f56f33
...@@ -6,6 +6,7 @@ provided by Arteris. ...@@ -6,6 +6,7 @@ provided by Arteris.
Required properties: Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family Should be "ti,omap4-l3-noc" for OMAP4 family
- reg: Contains L3 register address range for each noc domain.
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
Examples: Examples:
......
Documentation/devicetree/bindings/arm/omap/timer.txt
View file @ 38f56f33
OMAP Timer bindings OMAP Timer bindings
Required properties: Required properties:
- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers. - compatible: Should be set to one of the below. Please note that
OMAP44xx devices have timer instances that are 100%
register compatible with OMAP3xxx devices as well as
newer timers that are not 100% register compatible.
So for OMAP44xx devices timer instances may use
different compatible strings.
ti,omap2420-timer (applicable to OMAP24xx devices)
ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
ti,omap4430-timer (applicable to OMAP44xx devices)
ti,omap5430-timer (applicable to OMAP543x devices)
ti,am335x-timer (applicable to AM335x devices)
ti,am335x-timer-1ms (applicable to AM335x devices)
- reg: Contains timer register address range (base address and - reg: Contains timer register address range (base address and
length). length).
- interrupts: Contains the interrupt information for the timer. The - interrupts: Contains the interrupt information for the timer. The
...@@ -22,7 +35,7 @@ Optional properties: ...@@ -22,7 +35,7 @@ Optional properties:
Example: Example:
timer12: timer@48304000 { timer12: timer@48304000 {
compatible = "ti,omap2-timer"; compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>; reg = <0x48304000 0x400>;
interrupts = <95>; interrupts = <95>;
ti,hwmods = "timer12" ti,hwmods = "timer12"
......
Documentation/devicetree/bindings/arm/samsung/sysreg.txt 0 → 100644
View file @ 38f56f33
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
Properties:
- name : should be 'sysreg';
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
- reg : offset and length of the register set.
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
View file @ 38f56f33
...@@ -3,17 +3,58 @@ ...@@ -3,17 +3,58 @@
Required properties: Required properties:
- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx" - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
- reg : Should contain registers location and length - reg : Should contain registers location and length
- interrupts : Should contain the interrupt numbers of DMA channels.
If a channel is empty/reserved, 0 should be filled in place.
- #dma-cells : Must be <1>. The number cell specifies the channel ID.
- dma-channels : Number of channels supported by the DMA controller
Optional properties:
- interrupt-names : Name of DMA channel interrupts
Supported chips: Supported chips:
imx23, imx28. imx23, imx28.
Examples: Examples:
dma-apbh@80004000 {
dma_apbh: dma-apbh@80004000 {
compatible = "fsl,imx28-dma-apbh"; compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 2000>; reg = <0x80004000 0x2000>;
interrupts = <82 83 84 85
88 88 88 88
88 88 88 88
87 86 0 0>;
interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
"gpmi0", "gmpi1", "gpmi2", "gmpi3",
"gpmi4", "gmpi5", "gpmi6", "gmpi7",
"hsadc", "lcdif", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
}; };
dma-apbx@80024000 { dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx"; compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 2000>; reg = <0x80024000 0x2000>;
interrupts = <78 79 66 0
80 81 68 69
70 71 72 73
74 75 76 77>;
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
"saif0", "saif1", "i2c0", "i2c1",
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
#dma-cells = <1>;
dma-channels = <16>;
};
DMA clients connected to the MXS DMA controller must use the format
described in the dma.txt file.
Examples:
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
}; };
Documentation/devicetree/bindings/fb/mxsfb.txt
View file @ 38f56f33
...@@ -5,9 +5,16 @@ Required properties: ...@@ -5,9 +5,16 @@ Required properties:
imx23 and imx28. imx23 and imx28.
- reg: Address and length of the register set for lcdif - reg: Address and length of the register set for lcdif
- interrupts: Should contain lcdif interrupts - interrupts: Should contain lcdif interrupts
- display : phandle to display node (see below for details)
Optional properties: * display node
- panel-enable-gpios : Should specify the gpio for panel enable
Required properties:
- bits-per-pixel : <16> for RGB565, <32> for RGB888/666.
- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>.
Required sub-node:
- display-timings : Refer to binding doc display-timing.txt for details.
Examples: Examples:
...@@ -15,5 +22,28 @@ lcdif@80030000 { ...@@ -15,5 +22,28 @@ lcdif@80030000 {
compatible = "fsl,imx28-lcdif"; compatible = "fsl,imx28-lcdif";
reg = <0x80030000 2000>; reg = <0x80030000 2000>;
interrupts = <38 86>; interrupts = <38 86>;
panel-enable-gpios = <&gpio3 30 0>;
display: display {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <164>;
hback-porch = <89>;
hsync-len = <10>;
vback-porch = <23>;
vfront-porch = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
}; };
Documentation/devicetree/bindings/gpio/gpio-omap.txt
View file @ 38f56f33
...@@ -5,12 +5,12 @@ Required properties: ...@@ -5,12 +5,12 @@ Required properties:
- "ti,omap2-gpio" for OMAP2 controllers - "ti,omap2-gpio" for OMAP2 controllers
- "ti,omap3-gpio" for OMAP3 controllers - "ti,omap3-gpio" for OMAP3 controllers
- "ti,omap4-gpio" for OMAP4 controllers - "ti,omap4-gpio" for OMAP4 controllers
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. - #gpio-cells : Should be two.
- first cell is the pin number - first cell is the pin number
- second cell is used to specify optional parameters (unused) - second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller. - interrupt-controller: Mark the device node as an interrupt controller.
- #interrupt-cells : Should be 2. - #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
The first cell is the GPIO number. The first cell is the GPIO number.
The second cell is used to specify flags: The second cell is used to specify flags:
bits[3:0] trigger type and level flags: bits[3:0] trigger type and level flags:
...@@ -32,8 +32,8 @@ Example: ...@@ -32,8 +32,8 @@ Example:
gpio4: gpio4 { gpio4: gpio4 {
compatible = "ti,omap4-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4"; ti,hwmods = "gpio4";
#gpio-cells = <2>;
gpio-controller; gpio-controller;
#interrupt-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>;
}; };
Documentation/devicetree/bindings/gpu/samsung-g2d.txt 0 → 100644
View file @ 38f56f33
* Samsung 2D Graphics Accelerator
Required properties:
- compatible : value should be one among the following:
(a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC
(b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs
(c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
- interrupts : G2D interrupt number to the CPU.
Example:
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
};
Documentation/devicetree/bindings/i2c/i2c-mxs.txt
View file @ 38f56f33
...@@ -3,10 +3,13 @@ ...@@ -3,10 +3,13 @@
Required properties: Required properties:
- compatible: Should be "fsl,<chip>-i2c" - compatible: Should be "fsl,<chip>-i2c"
- reg: Should contain registers location and length - reg: Should contain registers location and length
- interrupts: Should contain ERROR and DMA interrupts - interrupts: Should contain ERROR interrupt number
- clock-frequency: Desired I2C bus clock frequency in Hz. - clock-frequency: Desired I2C bus clock frequency in Hz.
Only 100000Hz and 400000Hz modes are supported. Only 100000Hz and 400000Hz modes are supported.
- fsl,i2c-dma-channel: APBX DMA channel for the I2C - dmas: DMA specifier, consisting of a phandle to DMA controller node
and I2C DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Examples: Examples:
...@@ -15,7 +18,8 @@ i2c0: i2c@80058000 { ...@@ -15,7 +18,8 @@ i2c0: i2c@80058000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,imx28-i2c"; compatible = "fsl,imx28-i2c";
reg = <0x80058000 2000>; reg = <0x80058000 2000>;
interrupts = <111 68>; interrupts = <111>;
clock-frequency = <100000>; clock-frequency = <100000>;
fsl,i2c-dma-channel = <6>; dmas = <&dma_apbx 6>;
dma-names = "rx-tx";
}; };
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt 0 → 100644
View file @ 38f56f33
NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
Required properties:
- compatible : should be:
"nvidia,tegra114-i2c"
"nvidia,tegra30-i2c"
"nvidia,tegra20-i2c"
"nvidia,tegra20-i2c-dvc"
Details of compatible are as follows:
nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication. Register
interface/offset and interrupts handling are different than generic I2C
controller. Driver of DVC I2C controller is only compatible with
"nvidia,tegra20-i2c-dvc".
nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
master and slave mode of I2C communication. The i2c-tegra driver only
support master mode of I2C communication. Driver of I2C controller is
only compatible with "nvidia,tegra20-i2c".
nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
very much similar to Tegra20 I2C controller with additional feature:
Continue Transfer Support. This feature helps to implement M_NO_START
as per I2C core API transfer flags. Driver of I2C controller is
compatible with "nvidia,tegra30-i2c" to enable the continue transfer
support. This is also compatible with "nvidia,tegra20-i2c" without
continue transfer support.
nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
very much similar to Tegra30 I2C controller with some hardware
modification:
- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
fast-clk. Tegra114 has only one clock source called as div-clk and
hence clock mechanism is changed in I2C controller.
- Tegra30/Tegra20 I2C controller has enabled per packet transfer by
default and there is no way to disable it. Tegra114 has this
interrupt disable by default and SW need to enable explicitly.
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
- size-cells: Size of the I2C device address.
- clocks: Clock ID as per
Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
for I2C controller.
- clock-names: Name of the clock:
Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
Tegra114 I2C controller: "div-clk".
Example:
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};
Documentation/devicetree/bindings/mmc/mxs-mmc.txt
View file @ 38f56f33
...@@ -9,15 +9,19 @@ and the properties used by the mxsmmc driver. ...@@ -9,15 +9,19 @@ and the properties used by the mxsmmc driver.
Required properties: Required properties:
- compatible: Should be "fsl,<chip>-mmc". The supported chips include - compatible: Should be "fsl,<chip>-mmc". The supported chips include
imx23 and imx28. imx23 and imx28.
- interrupts: Should contain ERROR and DMA interrupts - interrupts: Should contain ERROR interrupt number
- fsl,ssp-dma-channel: APBH DMA channel for the SSP - dmas: DMA specifier, consisting of a phandle to DMA controller node
and SSP DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Examples: Examples:
ssp0: ssp@80010000 { ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc"; compatible = "fsl,imx28-mmc";
reg = <0x80010000 2000>; reg = <0x80010000 2000>;
interrupts = <96 82>; interrupts = <96>;
fsl,ssp-dma-channel = <0>; dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
bus-width = <8>; bus-width = <8>;
}; };
Documentation/devicetree/bindings/mtd/gpmi-nand.txt
View file @ 38f56f33
...@@ -7,10 +7,12 @@ Required properties: ...@@ -7,10 +7,12 @@ Required properties:
- compatible : should be "fsl,<chip>-gpmi-nand" - compatible : should be "fsl,<chip>-gpmi-nand"
- reg : should contain registers location and length for gpmi and bch. - reg : should contain registers location and length for gpmi and bch.
- reg-names: Should contain the reg names "gpmi-nand" and "bch" - reg-names: Should contain the reg names "gpmi-nand" and "bch"
- interrupts : The first is the DMA interrupt number for GPMI. - interrupts : BCH interrupt number.
The second is the BCH interrupt number. - interrupt-names : Should be "bch".
- interrupt-names : The interrupt names "gpmi-dma", "bch"; - dmas: DMA specifier, consisting of a phandle to DMA controller node
- fsl,gpmi-dma-channel : Should contain the dma channel it uses. and GPMI DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Optional properties: Optional properties:
- nand-on-flash-bbt: boolean to enable on flash bbt option if not - nand-on-flash-bbt: boolean to enable on flash bbt option if not
...@@ -27,9 +29,10 @@ gpmi-nand@8000c000 { ...@@ -27,9 +29,10 @@ gpmi-nand@8000c000 {
#size-cells = <1>; #size-cells = <1>;
reg = <0x8000c000 2000>, <0x8000a000 2000>; reg = <0x8000c000 2000>, <0x8000a000 2000>;
reg-names = "gpmi-nand", "bch"; reg-names = "gpmi-nand", "bch";
interrupts = <88>, <41>; interrupts = <41>;
interrupt-names = "gpmi-dma", "bch"; interrupt-names = "bch";
fsl,gpmi-dma-channel = <4>; dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
partition@0 { partition@0 {
... ...
......
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
View file @ 38f56f33
...@@ -70,6 +70,10 @@ Optional subnode-properties: ...@@ -70,6 +70,10 @@ Optional subnode-properties:
0: Disable the internal pull-up 0: Disable the internal pull-up
1: Enable the internal pull-up 1: Enable the internal pull-up
Note that when enabling the pull-up, the internal pad keeper gets disabled.
Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up
will only disable the internal pad keeper.
Examples: Examples:
pinctrl@80018000 { pinctrl@80018000 {
......
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
View file @ 38f56f33
...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex ...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties: Required properties:
- compatible : "nvidia,tegra-audio-alc5632" - compatible : "nvidia,tegra-audio-alc5632"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex. - nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components. - nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink, Each entry is a pair of strings, the first being the connection's sink,
...@@ -56,4 +61,7 @@ sound { ...@@ -56,4 +61,7 @@ sound {
nvidia,i2s-controller = <&tegra_i2s1>; nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&alc5632>; nvidia,audio-codec = <&alc5632>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
}; };
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt
View file @ 38f56f33
...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex for TrimSlice ...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex for TrimSlice
Required properties: Required properties:
- compatible : "nvidia,tegra-audio-trimslice" - compatible : "nvidia,tegra-audio-trimslice"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
- nvidia,audio-codec : The phandle of the WM8903 audio codec - nvidia,audio-codec : The phandle of the WM8903 audio codec
...@@ -11,4 +16,6 @@ sound { ...@@ -11,4 +16,6 @@ sound {
compatible = "nvidia,tegra-audio-trimslice"; compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>; nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>; nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
}; };
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
View file @ 38f56f33
...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex ...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties: Required properties:
- compatible : "nvidia,tegra-audio-wm8753" - compatible : "nvidia,tegra-audio-wm8753"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex. - nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components. - nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink, Each entry is a pair of strings, the first being the connection's sink,
...@@ -50,5 +55,8 @@ sound { ...@@ -50,5 +55,8 @@ sound {
nvidia,i2s-controller = <&i2s1>; nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8753>; nvidia,audio-codec = <&wm8753>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
}; };
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
View file @ 38f56f33
...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex ...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties: Required properties:
- compatible : "nvidia,tegra-audio-wm8903" - compatible : "nvidia,tegra-audio-wm8903"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex. - nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components. - nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink, Each entry is a pair of strings, the first being the connection's sink,
...@@ -67,5 +72,8 @@ sound { ...@@ -67,5 +72,8 @@ sound {
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
}; };
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
View file @ 38f56f33
...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex ...@@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties: Required properties:
- compatible : "nvidia,tegra-audio-wm9712" - compatible : "nvidia,tegra-audio-wm9712"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex. - nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components. - nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink, Each entry is a pair of strings, the first being the connection's sink,
...@@ -48,4 +53,7 @@ sound { ...@@ -48,4 +53,7 @@ sound {
"Mic", "MIC1"; "Mic", "MIC1";
nvidia,ac97-controller = <&ac97>; nvidia,ac97-controller = <&ac97>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
}; };
Documentation/devicetree/bindings/spi/mxs-spi.txt
View file @ 38f56f33
...@@ -3,8 +3,11 @@ ...@@ -3,8 +3,11 @@
Required properties: Required properties:
- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28" - compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"
- reg: Offset and length of the register set for the device - reg: Offset and length of the register set for the device
- interrupts: Should contain SSP interrupts (error irq first, dma irq second) - interrupts: Should contain SSP ERROR interrupt
- fsl,ssp-dma-channel: APBX DMA channel for the SSP - dmas: DMA specifier, consisting of a phandle to DMA controller node
and SSP DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Optional properties: Optional properties:
- clock-frequency : Input clock frequency to the SPI block in Hz. - clock-frequency : Input clock frequency to the SPI block in Hz.
...@@ -17,6 +20,7 @@ ssp0: ssp@80010000 { ...@@ -17,6 +20,7 @@ ssp0: ssp@80010000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,imx28-spi"; compatible = "fsl,imx28-spi";
reg = <0x80010000 0x2000>; reg = <0x80010000 0x2000>;
interrupts = <96 82>; interrupts = <96>;
fsl,ssp-dma-channel = <0>; dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
}; };
Documentation/devicetree/bindings/spi/spi-davinci.txt 0 → 100644
View file @ 38f56f33
Davinci SPI controller device bindings
Required properties:
- #address-cells: number of cells required to define a chip select
address on the SPI bus. Should be set to 1.
- #size-cells: should be zero.
- compatible:
- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
- reg: Offset and length of SPI controller register space
- num-cs: Number of chip selects
- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
IP to the interrupt controller within the SoC. Possible values
are 0 and 1. Manual says one of the two possible interrupt
lines can be tied to the interrupt controller. Set this
based on a specifc SoC configuration.
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
Example of a NOR flash slave device (n25q032) connected to DaVinci
SPI controller device over the SPI bus.
spi0:spi@20BF0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,dm6446-spi";
reg = <0x20BF0000 0x1000>;
num-cs = <4>;
ti,davinci-spi-intr-line = <0>;
interrupts = <338>;
clocks = <&clkspi>;
flash: n25q032@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32";
spi-max-frequency = <25000000>;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "test";
reg = <0x80000 0x380000>;
};
};
};
Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
View file @ 38f56f33
...@@ -5,20 +5,18 @@ Required properties: ...@@ -5,20 +5,18 @@ Required properties:
imx23 and imx28. imx23 and imx28.
- reg : Address and length of the register set for the device - reg : Address and length of the register set for the device
- interrupts : Should contain the auart interrupt numbers - interrupts : Should contain the auart interrupt numbers
- dmas: DMA specifier, consisting of a phandle to DMA controller node
Optional properties: and AUART DMA channel ID.
- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other Refer to dma.txt and fsl-mxs-dma.txt for details.
is for TX. If you add this property, it also means that you - dma-names: "rx" for RX channel, "tx" for TX channel.
will enable the DMA support for the auart.
Note: due to the hardware bug in imx23(see errata : 2836),
only the imx28 can enable the DMA support for the auart.
Example: Example:
auart0: serial@8006a000 { auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart"; compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>; reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>; interrupts = <112>;
fsl,auart-dma-channel = <8 9>; dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
}; };
Note: Each auart port should have an alias correctly numbered in "aliases" Note: Each auart port should have an alias correctly numbered in "aliases"
......
Documentation/devicetree/bindings/usb/exynos-usb.txt
View file @ 38f56f33
...@@ -10,6 +10,8 @@ Required properties: ...@@ -10,6 +10,8 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
- interrupts: interrupt number to the cpu. - interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
Optional properties: Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that - samsung,vbus-gpio: if present, specifies the GPIO that
...@@ -22,6 +24,9 @@ Example: ...@@ -22,6 +24,9 @@ Example:
reg = <0x12110000 0x100>; reg = <0x12110000 0x100>;
interrupts = <0 71 0>; interrupts = <0 71 0>;
samsung,vbus-gpio = <&gpx2 6 1 3 3>; samsung,vbus-gpio = <&gpx2 6 1 3 3>;
clocks = <&clock 285>;
clock-names = "usbhost";
}; };
OHCI OHCI
...@@ -31,10 +36,15 @@ Required properties: ...@@ -31,10 +36,15 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
- interrupts: interrupt number to the cpu. - interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
Example: Example:
usb@12120000 { usb@12120000 {
compatible = "samsung,exynos4210-ohci"; compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>; reg = <0x12120000 0x100>;
interrupts = <0 71 0>; interrupts = <0 71 0>;
clocks = <&clock 285>;
clock-names = "usbhost";
}; };
Documentation/devicetree/bindings/usb/omap-usb.txt
View file @ 38f56f33
...@@ -18,6 +18,7 @@ OMAP MUSB GLUE ...@@ -18,6 +18,7 @@ OMAP MUSB GLUE
represents PERIPHERAL. represents PERIPHERAL.
- power : Should be "50". This signifies the controller can supply upto - power : Should be "50". This signifies the controller can supply upto
100mA when operating in host mode. 100mA when operating in host mode.
- usb-phy : the phandle for the PHY device
Optional properties: Optional properties:
- ctrl-module : phandle of the control module this glue uses to write to - ctrl-module : phandle of the control module this glue uses to write to
......
Documentation/devicetree/bindings/video/samsung-fimd.txt 0 → 100644
View file @ 38f56f33
Device-Tree bindings for Samsung SoC display controller (FIMD)
FIMD (Fully Interactive Mobile Display) is the Display Controller for the
Samsung series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
"samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
"samsung,s5pc100-fimd"; /* for S5PC100 SoC */
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
- reg: physical base address and length of the FIMD registers set.
- interrupt-parent: should be the phandle of the fimd controller's
parent interrupt controller.
- interrupts: should contain a list of all FIMD IP block interrupts in the
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
- interrupt-names: should contain the interrupt names: "fifo", "vsync",
"lcd_sys", in the same order as they were listed in the interrupts
property.
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must contain a "default" entry.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "sclk_fimd" and "fimd".
Optional Properties:
- samsung,power-domain: a phandle to FIMD power domain node.
Example:
SoC specific DT entry:
fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock 140>, <&clock 283>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
status = "disabled";
};
Board specific DT entry:
fimd@11c00000 {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/Makefile
View file @ 38f56f33
...@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ ...@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4412-smdk4412.dtb \ exynos4412-smdk4412.dtb \
exynos4412-origen.dtb \ exynos4412-origen.dtb \
exynos5250-arndale.dtb \ exynos5250-arndale.dtb \
exynos5440-sd5v1.dtb \
exynos5250-smdk5250.dtb \ exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \ exynos5250-snow.dtb \
exynos5440-ssdk5440.dtb exynos5440-ssdk5440.dtb
...@@ -134,10 +135,14 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ ...@@ -134,10 +135,14 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-tx28.dtb imx28-tx28.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \ omap3-beagle.dtb \
omap3-devkit8000.dtb \
omap3-beagle-xm.dtb \ omap3-beagle-xm.dtb \
omap3-evm.dtb \ omap3-evm.dtb \
omap3-tobi.dtb \ omap3-tobi.dtb \
omap3-igep0020.dtb \
omap3-igep0030.dtb \
omap4-panda.dtb \ omap4-panda.dtb \
omap4-panda-a4.dtb \ omap4-panda-a4.dtb \
omap4-panda-es.dtb \ omap4-panda-es.dtb \
......
arch/arm/boot/dts/am335x-bone.dts
View file @ 38f56f33
...@@ -43,7 +43,7 @@ uart1: serial@44e09000 { ...@@ -43,7 +43,7 @@ uart1: serial@44e09000 {
status = "okay"; status = "okay";
}; };
i2c1: i2c@44e0b000 { i2c0: i2c@44e0b000 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
...@@ -59,27 +59,27 @@ leds { ...@@ -59,27 +59,27 @@ leds {
led@2 { led@2 {
label = "beaglebone:green:heartbeat"; label = "beaglebone:green:heartbeat";
gpios = <&gpio2 21 0>; gpios = <&gpio1 21 0>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
default-state = "off"; default-state = "off";
}; };
led@3 { led@3 {
label = "beaglebone:green:mmc0"; label = "beaglebone:green:mmc0";
gpios = <&gpio2 22 0>; gpios = <&gpio1 22 0>;
linux,default-trigger = "mmc0"; linux,default-trigger = "mmc0";
default-state = "off"; default-state = "off";
}; };
led@4 { led@4 {
label = "beaglebone:green:usr2"; label = "beaglebone:green:usr2";
gpios = <&gpio2 23 0>; gpios = <&gpio1 23 0>;
default-state = "off"; default-state = "off";
}; };
led@5 { led@5 {
label = "beaglebone:green:usr3"; label = "beaglebone:green:usr3";
gpios = <&gpio2 24 0>; gpios = <&gpio1 24 0>;
default-state = "off"; default-state = "off";
}; };
}; };
......
arch/arm/boot/dts/am335x-evm.dts
View file @ 38f56f33
...@@ -51,7 +51,7 @@ uart1: serial@44e09000 { ...@@ -51,7 +51,7 @@ uart1: serial@44e09000 {
status = "okay"; status = "okay";
}; };
i2c1: i2c@44e0b000 { i2c0: i2c@44e0b000 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
...@@ -60,7 +60,7 @@ tps: tps@2d { ...@@ -60,7 +60,7 @@ tps: tps@2d {
}; };
}; };
i2c2: i2c@4802a000 { i2c1: i2c@4802a000 {
status = "okay"; status = "okay";
clock-frequency = <100000>; clock-frequency = <100000>;
...@@ -123,12 +123,12 @@ matrix_keypad: matrix_keypad@0 { ...@@ -123,12 +123,12 @@ matrix_keypad: matrix_keypad@0 {
debounce-delay-ms = <5>; debounce-delay-ms = <5>;
col-scan-delay-us = <2>; col-scan-delay-us = <2>;
row-gpios = <&gpio2 25 0 /* Bank1, pin25 */ row-gpios = <&gpio1 25 0 /* Bank1, pin25 */
&gpio2 26 0 /* Bank1, pin26 */ &gpio1 26 0 /* Bank1, pin26 */
&gpio2 27 0>; /* Bank1, pin27 */ &gpio1 27 0>; /* Bank1, pin27 */
col-gpios = <&gpio2 21 0 /* Bank1, pin21 */ col-gpios = <&gpio1 21 0 /* Bank1, pin21 */
&gpio2 22 0>; /* Bank1, pin22 */ &gpio1 22 0>; /* Bank1, pin22 */
linux,keymap = <0x0000008b /* MENU */ linux,keymap = <0x0000008b /* MENU */
0x0100009e /* BACK */ 0x0100009e /* BACK */
...@@ -147,14 +147,14 @@ gpio_keys: volume_keys@0 { ...@@ -147,14 +147,14 @@ gpio_keys: volume_keys@0 {
switch@9 { switch@9 {
label = "volume-up"; label = "volume-up";
linux,code = <115>; linux,code = <115>;
gpios = <&gpio1 2 1>; gpios = <&gpio0 2 1>;
gpio-key,wakeup; gpio-key,wakeup;
}; };
switch@10 { switch@10 {
label = "volume-down"; label = "volume-down";
linux,code = <114>; linux,code = <114>;
gpios = <&gpio1 3 1>; gpios = <&gpio0 3 1>;
gpio-key,wakeup; gpio-key,wakeup;
}; };
}; };
......
arch/arm/boot/dts/am335x-evmsk.dts
View file @ 38f56f33
...@@ -58,7 +58,7 @@ uart1: serial@44e09000 { ...@@ -58,7 +58,7 @@ uart1: serial@44e09000 {
status = "okay"; status = "okay";
}; };
i2c1: i2c@44e0b000 { i2c0: i2c@44e0b000 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
...@@ -115,26 +115,26 @@ leds { ...@@ -115,26 +115,26 @@ leds {
led@1 { led@1 {
label = "evmsk:green:usr0"; label = "evmsk:green:usr0";
gpios = <&gpio2 4 0>; gpios = <&gpio1 4 0>;
default-state = "off"; default-state = "off";
}; };
led@2 { led@2 {
label = "evmsk:green:usr1"; label = "evmsk:green:usr1";
gpios = <&gpio2 5 0>; gpios = <&gpio1 5 0>;
default-state = "off"; default-state = "off";
}; };
led@3 { led@3 {
label = "evmsk:green:mmc0"; label = "evmsk:green:mmc0";
gpios = <&gpio2 6 0>; gpios = <&gpio1 6 0>;
linux,default-trigger = "mmc0"; linux,default-trigger = "mmc0";
default-state = "off"; default-state = "off";
}; };
led@4 { led@4 {
label = "evmsk:green:heartbeat"; label = "evmsk:green:heartbeat";
gpios = <&gpio2 7 0>; gpios = <&gpio1 7 0>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
default-state = "off"; default-state = "off";
}; };
...@@ -148,26 +148,26 @@ gpio_buttons: gpio_buttons@0 { ...@@ -148,26 +148,26 @@ gpio_buttons: gpio_buttons@0 {
switch@1 { switch@1 {
label = "button0"; label = "button0";
linux,code = <0x100>; linux,code = <0x100>;
gpios = <&gpio3 3 0>; gpios = <&gpio2 3 0>;
}; };
switch@2 { switch@2 {
label = "button1"; label = "button1";
linux,code = <0x101>; linux,code = <0x101>;
gpios = <&gpio3 2 0>; gpios = <&gpio2 2 0>;
}; };
switch@3 { switch@3 {
label = "button2"; label = "button2";
linux,code = <0x102>; linux,code = <0x102>;
gpios = <&gpio1 30 0>; gpios = <&gpio0 30 0>;
gpio-key,wakeup; gpio-key,wakeup;
}; };
switch@4 { switch@4 {
label = "button3"; label = "button3";
linux,code = <0x103>; linux,code = <0x103>;
gpios = <&gpio3 5 0>; gpios = <&gpio2 5 0>;
}; };
}; };
}; };
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 38f56f33
...@@ -21,6 +21,8 @@ aliases { ...@@ -21,6 +21,8 @@ aliases {
serial3 = &uart4; serial3 = &uart4;
serial4 = &uart5; serial4 = &uart5;
serial5 = &uart6; serial5 = &uart6;
d_can0 = &dcan0;
d_can1 = &dcan1;
}; };
cpus { cpus {
...@@ -87,7 +89,7 @@ intc: interrupt-controller@48200000 { ...@@ -87,7 +89,7 @@ intc: interrupt-controller@48200000 {
reg = <0x48200000 0x1000>; reg = <0x48200000 0x1000>;
}; };
gpio1: gpio@44e07000 { gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1"; ti,hwmods = "gpio1";
gpio-controller; gpio-controller;
...@@ -98,7 +100,7 @@ gpio1: gpio@44e07000 { ...@@ -98,7 +100,7 @@ gpio1: gpio@44e07000 {
interrupts = <96>; interrupts = <96>;
}; };
gpio2: gpio@4804c000 { gpio1: gpio@4804c000 {
compatible = "ti,omap4-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2"; ti,hwmods = "gpio2";
gpio-controller; gpio-controller;
...@@ -109,7 +111,7 @@ gpio2: gpio@4804c000 { ...@@ -109,7 +111,7 @@ gpio2: gpio@4804c000 {
interrupts = <98>; interrupts = <98>;
}; };
gpio3: gpio@481ac000 { gpio2: gpio@481ac000 {
compatible = "ti,omap4-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3"; ti,hwmods = "gpio3";
gpio-controller; gpio-controller;
...@@ -120,7 +122,7 @@ gpio3: gpio@481ac000 { ...@@ -120,7 +122,7 @@ gpio3: gpio@481ac000 {
interrupts = <32>; interrupts = <32>;
}; };
gpio4: gpio@481ae000 { gpio3: gpio@481ae000 {
compatible = "ti,omap4-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4"; ti,hwmods = "gpio4";
gpio-controller; gpio-controller;
...@@ -185,7 +187,7 @@ uart6: serial@481aa000 { ...@@ -185,7 +187,7 @@ uart6: serial@481aa000 {
status = "disabled"; status = "disabled";
}; };
i2c1: i2c@44e0b000 { i2c0: i2c@44e0b000 {
compatible = "ti,omap4-i2c"; compatible = "ti,omap4-i2c";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -195,7 +197,7 @@ i2c1: i2c@44e0b000 { ...@@ -195,7 +197,7 @@ i2c1: i2c@44e0b000 {
status = "disabled"; status = "disabled";
}; };
i2c2: i2c@4802a000 { i2c1: i2c@4802a000 {
compatible = "ti,omap4-i2c"; compatible = "ti,omap4-i2c";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -205,7 +207,7 @@ i2c2: i2c@4802a000 { ...@@ -205,7 +207,7 @@ i2c2: i2c@4802a000 {
status = "disabled"; status = "disabled";
}; };
i2c3: i2c@4819c000 { i2c2: i2c@4819c000 {
compatible = "ti,omap4-i2c"; compatible = "ti,omap4-i2c";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -225,7 +227,8 @@ wdt2: wdt@44e35000 { ...@@ -225,7 +227,8 @@ wdt2: wdt@44e35000 {
dcan0: d_can@481cc000 { dcan0: d_can@481cc000 {
compatible = "bosch,d_can"; compatible = "bosch,d_can";
ti,hwmods = "d_can0"; ti,hwmods = "d_can0";
reg = <0x481cc000 0x2000>; reg = <0x481cc000 0x2000
0x44e10644 0x4>;
interrupts = <52>; interrupts = <52>;
status = "disabled"; status = "disabled";
}; };
...@@ -233,13 +236,14 @@ dcan0: d_can@481cc000 { ...@@ -233,13 +236,14 @@ dcan0: d_can@481cc000 {
dcan1: d_can@481d0000 { dcan1: d_can@481d0000 {
compatible = "bosch,d_can"; compatible = "bosch,d_can";
ti,hwmods = "d_can1"; ti,hwmods = "d_can1";
reg = <0x481d0000 0x2000>; reg = <0x481d0000 0x2000
0x44e10644 0x4>;
interrupts = <55>; interrupts = <55>;
status = "disabled"; status = "disabled";
}; };
timer1: timer@44e31000 { timer1: timer@44e31000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>; reg = <0x44e31000 0x400>;
interrupts = <67>; interrupts = <67>;
ti,hwmods = "timer1"; ti,hwmods = "timer1";
...@@ -247,21 +251,21 @@ timer1: timer@44e31000 { ...@@ -247,21 +251,21 @@ timer1: timer@44e31000 {
}; };
timer2: timer@48040000 { timer2: timer@48040000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer";
reg = <0x48040000 0x400>; reg = <0x48040000 0x400>;
interrupts = <68>; interrupts = <68>;
ti,hwmods = "timer2"; ti,hwmods = "timer2";
}; };
timer3: timer@48042000 { timer3: timer@48042000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer";
reg = <0x48042000 0x400>; reg = <0x48042000 0x400>;
interrupts = <69>; interrupts = <69>;
ti,hwmods = "timer3"; ti,hwmods = "timer3";
}; };
timer4: timer@48044000 { timer4: timer@48044000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer";
reg = <0x48044000 0x400>; reg = <0x48044000 0x400>;
interrupts = <92>; interrupts = <92>;
ti,hwmods = "timer4"; ti,hwmods = "timer4";
...@@ -269,7 +273,7 @@ timer4: timer@48044000 { ...@@ -269,7 +273,7 @@ timer4: timer@48044000 {
}; };
timer5: timer@48046000 { timer5: timer@48046000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer";
reg = <0x48046000 0x400>; reg = <0x48046000 0x400>;
interrupts = <93>; interrupts = <93>;
ti,hwmods = "timer5"; ti,hwmods = "timer5";
...@@ -277,7 +281,7 @@ timer5: timer@48046000 { ...@@ -277,7 +281,7 @@ timer5: timer@48046000 {
}; };
timer6: timer@48048000 { timer6: timer@48048000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer";
reg = <0x48048000 0x400>; reg = <0x48048000 0x400>;
interrupts = <94>; interrupts = <94>;
ti,hwmods = "timer6"; ti,hwmods = "timer6";
...@@ -285,7 +289,7 @@ timer6: timer@48048000 { ...@@ -285,7 +289,7 @@ timer6: timer@48048000 {
}; };
timer7: timer@4804a000 { timer7: timer@4804a000 {
compatible = "ti,omap2-timer"; compatible = "ti,am335x-timer";
reg = <0x4804a000 0x400>; reg = <0x4804a000 0x400>;
interrupts = <95>; interrupts = <95>;
ti,hwmods = "timer7"; ti,hwmods = "timer7";
...@@ -305,7 +309,7 @@ spi0: spi@48030000 { ...@@ -305,7 +309,7 @@ spi0: spi@48030000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x48030000 0x400>; reg = <0x48030000 0x400>;
interrupt = <65>; interrupts = <65>;
ti,spi-num-cs = <2>; ti,spi-num-cs = <2>;
ti,hwmods = "spi0"; ti,hwmods = "spi0";
status = "disabled"; status = "disabled";
...@@ -316,7 +320,7 @@ spi1: spi@481a0000 { ...@@ -316,7 +320,7 @@ spi1: spi@481a0000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x481a0000 0x400>; reg = <0x481a0000 0x400>;
interrupt = <125>; interrupts = <125>;
ti,spi-num-cs = <2>; ti,spi-num-cs = <2>;
ti,hwmods = "spi1"; ti,hwmods = "spi1";
status = "disabled"; status = "disabled";
......
arch/arm/boot/dts/am3517-evm.dts
View file @ 38f56f33
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
*/ */
/dts-v1/; /dts-v1/;
/include/ "omap3.dtsi" /include/ "omap34xx.dtsi"
/ { / {
model = "TI AM3517 EVM (AM3517/05)"; model = "TI AM3517 EVM (AM3517/05)";
......
arch/arm/boot/dts/am3517_mt_ventoux.dts
View file @ 38f56f33
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
*/ */
/dts-v1/; /dts-v1/;
/include/ "omap3.dtsi" /include/ "omap34xx.dtsi"
/ { / {
model = "TeeJet Mt.Ventoux"; model = "TeeJet Mt.Ventoux";
......
arch/arm/boot/dts/armada-370-db.dts
View file @ 38f56f33
...@@ -30,85 +30,87 @@ memory { ...@@ -30,85 +30,87 @@ memory {
}; };
soc { soc {
serial@d0012000 { internal-regs {
clock-frequency = <200000000>; serial@12000 {
status = "okay"; clock-frequency = <200000000>;
}; status = "okay";
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
}; };
sata@a0000 {
phy1: ethernet-phy@1 { nr-ports = <2>;
reg = <1>; status = "okay";
}; };
};
ethernet@d0070000 { mdio {
status = "okay"; phy0: ethernet-phy@0 {
phy = <&phy0>; reg = <0>;
phy-mode = "rgmii-id"; };
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d00d4000 { phy1: ethernet-phy@1 {
pinctrl-0 = <&sdio_pins1>; reg = <1>;
pinctrl-names = "default"; };
/* };
* This device is disabled by default, because
* using the SD card connector requires
* changing the default CON40 connector
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
* different connector
* "DB-88F6710_MPP_RGMII_SD_Jumper".
*/
status = "disabled";
/* No CD or WP GPIOs */
};
usb@d0050000 { ethernet@70000 {
status = "okay"; status = "okay";
}; phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
usb@d0051000 { mvsdio@d4000 {
status = "okay"; pinctrl-0 = <&sdio_pins1>;
}; pinctrl-names = "default";
/*
* This device is disabled by default, because
* using the SD card connector requires
* changing the default CON40 connector
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
* different connector
* "DB-88F6710_MPP_RGMII_SD_Jumper".
*/
status = "disabled";
/* No CD or WP GPIOs */
};
spi0: spi@d0010600 { usb@50000 {
status = "okay"; status = "okay";
};
spi-flash@0 { usb@51000 {
#address-cells = <1>; status = "okay";
#size-cells = <1>;
compatible = "mx25l25635e";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
}; };
};
pcie-controller { spi0: spi@10600 {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
};
}; };
pcie@2,0 {
/* Port 1, Lane 0 */ pcie-controller {
status = "okay"; status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-370-mirabox.dts
View file @ 38f56f33
...@@ -25,113 +25,115 @@ memory { ...@@ -25,113 +25,115 @@ memory {
}; };
soc { soc {
serial@d0012000 { internal-regs {
clock-frequency = <200000000>; serial@12000 {
status = "okay"; clock-frequency = <200000000>;
}; status = "okay";
timer@d0020300 {
clock-frequency = <600000000>;
status = "okay";
};
pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";
marvell,function = "gpo";
}; };
timer@20300 {
stat_led_pins: stat-led-pins { clock-frequency = <600000000>;
marvell,pins = "mpp64", "mpp65"; status = "okay";
marvell,function = "gpio";
}; };
};
gpio_leds { pinctrl {
compatible = "gpio-leds"; pwr_led_pin: pwr-led-pin {
pinctrl-names = "default"; marvell,pins = "mpp63";
pinctrl-0 = <&pwr_led_pin &stat_led_pins>; marvell,function = "gpo";
};
green_pwr_led { stat_led_pins: stat-led-pins {
label = "mirabox:green:pwr"; marvell,pins = "mpp64", "mpp65";
gpios = <&gpio1 31 1>; marvell,function = "gpio";
linux,default-trigger = "heartbeat"; };
}; };
blue_stat_led { gpio_leds {
label = "mirabox:blue:stat"; compatible = "gpio-leds";
gpios = <&gpio2 0 1>; pinctrl-names = "default";
linux,default-trigger = "cpu0"; pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
green_pwr_led {
label = "mirabox:green:pwr";
gpios = <&gpio1 31 1>;
linux,default-trigger = "heartbeat";
};
blue_stat_led {
label = "mirabox:blue:stat";
gpios = <&gpio2 0 1>;
linux,default-trigger = "cpu0";
};
green_stat_led {
label = "mirabox:green:stat";
gpios = <&gpio2 1 1>;
default-state = "off";
};
}; };
green_stat_led { mdio {
label = "mirabox:green:stat"; phy0: ethernet-phy@0 {
gpios = <&gpio2 1 1>; reg = <0>;
default-state = "off"; };
};
};
mdio { phy1: ethernet-phy@1 {
phy0: ethernet-phy@0 { reg = <1>;
reg = <0>; };
}; };
ethernet@70000 {
phy1: ethernet-phy@1 { status = "okay";
reg = <1>; phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
}; };
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
status = "okay";
/*
* No CD or WP GPIOs: SDIO interface used for
* Wifi/Bluetooth chip
*/
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 { mvsdio@d4000 {
status = "okay"; pinctrl-0 = <&sdio_pins3>;
}; pinctrl-names = "default";
status = "okay";
/*
* No CD or WP GPIOs: SDIO interface used for
* Wifi/Bluetooth chip
*/
};
i2c@d0011000 { usb@50000 {
status = "okay"; status = "okay";
clock-frequency = <100000>;
pca9505: pca9505@25 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x25>;
}; };
};
pcie-controller { usb@51000 {
status = "okay"; status = "okay";
};
/* Internal mini-PCIe connector */ i2c@11000 {
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
clock-frequency = <100000>;
pca9505: pca9505@25 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x25>;
};
}; };
/* Connected on the PCB to a USB 3.0 XHCI controller */ pcie-controller {
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay"; status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-370-rd.dts
View file @ 38f56f33
...@@ -28,60 +28,62 @@ memory { ...@@ -28,60 +28,62 @@ memory {
}; };
soc { soc {
serial@d0012000 { internal-regs {
clock-frequency = <200000000>; serial@12000 {
status = "okay"; clock-frequency = <200000000>;
}; status = "okay";
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
}; };
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
reg = <1>; reg = <1>;
};
}; };
};
ethernet@d0070000 { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>; phy = <&phy0>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@d0074000 { ethernet@74000 {
status = "okay"; status = "okay";
phy = <&phy1>; phy = <&phy1>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
}; };
mvsdio@d00d4000 { mvsdio@d4000 {
pinctrl-0 = <&sdio_pins1>; pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
/* No CD or WP GPIOs */ /* No CD or WP GPIOs */
}; };
usb@d0050000 { usb@50000 {
status = "okay"; status = "okay";
}; };
usb@d0051000 { usb@51000 {
status = "okay"; status = "okay";
}; };
};
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
button@1 { button@1 {
label = "Software Button"; label = "Software Button";
linux,code = <116>; linux,code = <116>;
gpios = <&gpio0 6 1>; gpios = <&gpio0 6 1>;
};
};
}; };
}; };
}; };
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ 38f56f33
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
* 370 and Armada XP SoC. * 370 and Armada XP SoC.
*/ */
/include/ "skeleton.dtsi" /include/ "skeleton64.dtsi"
/ { / {
model = "Marvell Armada 370 and XP SoC"; model = "Marvell Armada 370 and XP SoC";
...@@ -28,199 +28,203 @@ cpu@0 { ...@@ -28,199 +28,203 @@ cpu@0 {
}; };
}; };
mpic: interrupt-controller@d0020000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
};
coherency-fabric@d0020200 {
compatible = "marvell,coherency-fabric";
reg = <0xd0020200 0xb0>,
<0xd0021810 0x1c>;
};
soc { soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
ranges; ranges = <0 0 0xd0000000 0x100000>;
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
};
coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21810 0x1c>;
};
serial@d0012000 { serial@12000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0xd0012000 0x100>; reg = <0x12000 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <41>; interrupts = <41>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
serial@d0012100 { serial@12100 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0xd0012100 0x100>; reg = <0x12100 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <42>; interrupts = <42>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
timer@d0020300 { timer@20300 {
compatible = "marvell,armada-370-xp-timer"; compatible = "marvell,armada-370-xp-timer";
reg = <0xd0020300 0x30>, reg = <0x20300 0x30>, <0x21040 0x30>;
<0xd0021040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>; clocks = <&coreclk 2>;
clocks = <&coreclk 2>; };
};
sata@a0000 {
sata@d00a0000 { compatible = "marvell,orion-sata";
compatible = "marvell,orion-sata"; reg = <0xa0000 0x2400>;
reg = <0xd00a0000 0x2400>; interrupts = <55>;
interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>;
clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1";
clock-names = "0", "1"; status = "disabled";
status = "disabled"; };
};
mdio { mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "marvell,orion-mdio"; compatible = "marvell,orion-mdio";
reg = <0xd0072004 0x4>; reg = <0x72004 0x4>;
}; };
ethernet@d0070000 { ethernet@70000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0xd0070000 0x2500>; reg = <0x70000 0x2500>;
interrupts = <8>; interrupts = <8>;
clocks = <&gateclk 4>; clocks = <&gateclk 4>;
status = "disabled"; status = "disabled";
}; };
ethernet@d0074000 { ethernet@74000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0xd0074000 0x2500>; reg = <0x74000 0x2500>;
interrupts = <10>; interrupts = <10>;
clocks = <&gateclk 3>; clocks = <&gateclk 3>;
status = "disabled"; status = "disabled";
}; };
i2c0: i2c@d0011000 { i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c"; compatible = "marvell,mv64xxx-i2c";
reg = <0xd0011000 0x20>; reg = <0x11000 0x20>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <31>; interrupts = <31>;
timeout-ms = <1000>; timeout-ms = <1000>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
i2c1: i2c@d0011100 { i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c"; compatible = "marvell,mv64xxx-i2c";
reg = <0xd0011100 0x20>; reg = <0x11100 0x20>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <32>; interrupts = <32>;
timeout-ms = <1000>; timeout-ms = <1000>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
rtc@10300 { rtc@10300 {
compatible = "marvell,orion-rtc"; compatible = "marvell,orion-rtc";
reg = <0xd0010300 0x20>; reg = <0x10300 0x20>;
interrupts = <50>; interrupts = <50>;
}; };
mvsdio@d00d4000 { mvsdio@d4000 {
compatible = "marvell,orion-sdio"; compatible = "marvell,orion-sdio";
reg = <0xd00d4000 0x200>; reg = <0xd4000 0x200>;
interrupts = <54>; interrupts = <54>;
clocks = <&gateclk 17>; clocks = <&gateclk 17>;
status = "disabled"; status = "disabled";
}; };
usb@d0050000 {
compatible = "marvell,orion-ehci";
reg = <0xd0050000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@d0051000 {
compatible = "marvell,orion-ehci";
reg = <0xd0051000 0x500>;
interrupts = <46>;
status = "disabled";
};
spi0: spi@d0010600 {
compatible = "marvell,orion-spi";
reg = <0xd0010600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@d0010680 {
compatible = "marvell,orion-spi";
reg = <0xd0010680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-bootcs@d0010400 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0@d0010408 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1@d0010410 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2@d0010418 { usb@50000 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,orion-ehci";
reg = <0xd0010418 0x8>; reg = <0x50000 0x500>;
#address-cells = <1>; interrupts = <45>;
#size-cells = <1>; status = "disabled";
clocks = <&coreclk 0>; };
status = "disabled";
};
devbus-cs3@d0010420 { usb@51000 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,orion-ehci";
reg = <0xd0010420 0x8>; reg = <0x51000 0x500>;
#address-cells = <1>; interrupts = <46>;
#size-cells = <1>; status = "disabled";
clocks = <&coreclk 0>; };
status = "disabled";
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-bootcs@10400 {
compatible = "marvell,mvebu-devbus";
reg = <0x10400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0@10408 {
compatible = "marvell,mvebu-devbus";
reg = <0x10408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1@10410 {
compatible = "marvell,mvebu-devbus";
reg = <0x10410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2@10418 {
compatible = "marvell,mvebu-devbus";
reg = <0x10418 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3@10420 {
compatible = "marvell,mvebu-devbus";
reg = <0x10420 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
}; };
}; };
}; };
arch/arm/boot/dts/armada-370.dtsi
View file @ 38f56f33
...@@ -16,16 +16,11 @@ ...@@ -16,16 +16,11 @@
*/ */
/include/ "armada-370-xp.dtsi" /include/ "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"
/ { / {
model = "Marvell Armada 370 family SoC"; model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp"; compatible = "marvell,armada370", "marvell,armada-370-xp";
L2: l2-cache {
compatible = "marvell,aurora-outer-cache";
reg = <0xd0008000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};
aliases { aliases {
gpio0 = &gpio0; gpio0 = &gpio0;
...@@ -33,188 +28,197 @@ aliases { ...@@ -33,188 +28,197 @@ aliases {
gpio2 = &gpio2; gpio2 = &gpio2;
}; };
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x1d0>,
<0xd0021870 0x58>;
};
soc { soc {
system-controller@d0018200 { ranges = <0 0xd0000000 0x100000>;
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller"; compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>; reg = <0x18200 0x100>;
};
pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
reg = <0xd0018000 0x38>;
sdio_pins1: sdio-pins1 {
marvell,pins = "mpp9", "mpp11", "mpp12",
"mpp13", "mpp14", "mpp15";
marvell,function = "sd0";
}; };
sdio_pins2: sdio-pins2 { L2: l2-cache {
marvell,pins = "mpp47", "mpp48", "mpp49", compatible = "marvell,aurora-outer-cache";
"mpp50", "mpp51", "mpp52"; reg = <0xd0008000 0x1000>;
marvell,function = "sd0"; cache-id-part = <0x100>;
wt-override;
}; };
sdio_pins3: sdio-pins3 { mpic: interrupt-controller@20000 {
marvell,pins = "mpp48", "mpp49", "mpp50", reg = <0x20a00 0x1d0>, <0x21870 0x58>;
"mpp51", "mpp52", "mpp53";
marvell,function = "sd0";
}; };
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
coreclk: mvebu-sar@d0018230 { pinctrl {
compatible = "marvell,armada-370-core-clock"; compatible = "marvell,mv88f6710-pinctrl";
reg = <0xd0018230 0x08>; reg = <0x18000 0x38>;
#clock-cells = <1>;
}; sdio_pins1: sdio-pins1 {
marvell,pins = "mpp9", "mpp11", "mpp12",
gateclk: clock-gating-control@d0018220 { "mpp13", "mpp14", "mpp15";
compatible = "marvell,armada-370-gating-clock"; marvell,function = "sd0";
reg = <0xd0018220 0x4>; };
clocks = <&coreclk 0>;
#clock-cells = <1>; sdio_pins2: sdio-pins2 {
}; marvell,pins = "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52";
xor@d0060800 { marvell,function = "sd0";
compatible = "marvell,orion-xor"; };
reg = <0xd0060800 0x100
0xd0060A00 0x100>; sdio_pins3: sdio-pins3 {
status = "okay"; marvell,pins = "mpp48", "mpp49", "mpp50",
"mpp51", "mpp52", "mpp53";
xor00 { marvell,function = "sd0";
interrupts = <51>; };
dmacap,memcpy;
dmacap,xor;
}; };
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor@d0060900 {
compatible = "marvell,orion-xor";
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
status = "okay";
xor10 { gpio0: gpio@18100 {
interrupts = <94>; compatible = "marvell,orion-gpio";
dmacap,memcpy; reg = <0x18100 0x40>;
dmacap,xor; ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
}; };
xor11 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
usb@d0050000 { gpio1: gpio@18140 {
clocks = <&coreclk 0>; compatible = "marvell,orion-gpio";
}; reg = <0x18140 0x40>;
ngpios = <32>;
usb@d0051000 { gpio-controller;
clocks = <&coreclk 0>; #gpio-cells = <2>;
}; interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
thermal@d0018300 { gpio2: gpio@18180 {
compatible = "marvell,armada370-thermal"; compatible = "marvell,orion-gpio";
reg = <0xd0018300 0x4 reg = <0x18180 0x40>;
0xd0018304 0x4>; ngpios = <2>;
status = "okay"; gpio-controller;
}; #gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
pcie-controller { coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-370-pcie"; compatible = "marvell,armada-370-core-clock";
status = "disabled"; reg = <0x18230 0x08>;
device_type = "pci"; #clock-cells = <1>;
};
#address-cells = <3>; gateclk: clock-gating-control@18220 {
#size-cells = <2>; compatible = "marvell,armada-370-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
bus-range = <0x00 0xff>; xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
status = "okay";
xor00 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>; xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
status = "okay";
xor10 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
reg-names = "pcie0.0", "pcie1.0"; usb@50000 {
clocks = <&coreclk 0>;
};
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ usb@51000 {
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ clocks = <&coreclk 0>;
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ };
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 { thermal@18300 {
device_type = "pci"; compatible = "marvell,armada370-thermal";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; reg = <0x18300 0x4
reg = <0x0800 0 0 0 0>; 0x18304 0x4>;
#address-cells = <3>; status = "okay";
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
}; };
pcie@2,0 { pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>;
ranges; bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>; reg = <0x40000 0x2000>, <0x80000 0x2000>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>; reg-names = "pcie0.0", "pcie1.0";
clocks = <&gateclk 9>;
status = "disabled"; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-db.dts
View file @ 38f56f33
...@@ -26,132 +26,134 @@ chosen { ...@@ -26,132 +26,134 @@ chosen {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */ reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
}; };
soc { soc {
serial@d0012000 { internal-regs {
clock-frequency = <250000000>; serial@12000 {
status = "okay"; clock-frequency = <250000000>;
}; status = "okay";
serial@d0012100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
}; };
serial@12100 {
phy1: ethernet-phy@1 { clock-frequency = <250000000>;
reg = <1>; status = "okay";
}; };
serial@12200 {
phy2: ethernet-phy@2 { clock-frequency = <250000000>;
reg = <25>; status = "okay";
}; };
serial@12300 {
phy3: ethernet-phy@3 { clock-frequency = <250000000>;
reg = <27>; status = "okay";
}; };
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@d0030000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@d0034000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};
usb@d0050000 { sata@a0000 {
status = "okay"; nr-ports = <2>;
}; status = "okay";
};
usb@d0051000 { mdio {
status = "okay"; phy0: ethernet-phy@0 {
}; reg = <0>;
};
usb@d0052000 { phy1: ethernet-phy@1 {
status = "okay"; reg = <1>;
}; };
spi0: spi@d0010600 { phy2: ethernet-phy@2 {
status = "okay"; reg = <25>;
};
spi-flash@0 { phy3: ethernet-phy@3 {
#address-cells = <1>; reg = <27>;
#size-cells = <1>; };
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
}; };
};
pcie-controller { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
/* mvsdio@d4000 {
* All 6 slots are physically present as pinctrl-0 = <&sdio_pins>;
* standard PCIe slots on the board. pinctrl-names = "default";
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
/* No CD or WP GPIOs */
}; };
pcie@2,0 {
/* Port 0, Lane 1 */ usb@50000 {
status = "okay"; status = "okay";
}; };
pcie@3,0 {
/* Port 0, Lane 2 */ usb@51000 {
status = "okay"; status = "okay";
}; };
pcie@4,0 {
/* Port 0, Lane 3 */ usb@52000 {
status = "okay"; status = "okay";
}; };
pcie@9,0 {
/* Port 2, Lane 0 */ spi0: spi@10600 {
status = "okay"; status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
};
}; };
pcie@10,0 {
/* Port 3, Lane 0 */ pcie-controller {
status = "okay"; status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-gp.dts
View file @ 38f56f33
...@@ -26,137 +26,141 @@ chosen { ...@@ -26,137 +26,141 @@ chosen {
memory { memory {
device_type = "memory"; device_type = "memory";
/* /*
* 4 GB of plug-in RAM modules by default but only 3GB * 8 GB of plug-in RAM modules by default.The amount
* are visible, the amount of memory available can be * of memory available can be changed by the
* changed by the bootloader according the size of the * bootloader according the size of the module
* module actually plugged * actually plugged. Only 7GB are usable because
* addresses from 0xC0000000 to 0xffffffff are used by
* the internal registers of the SoC.
*/ */
reg = <0x00000000 0xC0000000>; reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
<0x00000001 0x00000000 0x00000001 0x00000000>;
}; };
soc { soc {
serial@d0012000 { internal-regs {
clock-frequency = <250000000>; serial@12000 {
status = "okay"; clock-frequency = <250000000>;
}; status = "okay";
serial@d0012100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
}; };
serial@12100 {
phy1: ethernet-phy@1 { clock-frequency = <250000000>;
reg = <17>; status = "okay";
}; };
serial@12200 {
phy2: ethernet-phy@2 { clock-frequency = <250000000>;
reg = <18>; status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
}; };
phy3: ethernet-phy@3 { sata@a0000 {
reg = <19>; nr-ports = <2>;
status = "okay";
}; };
};
ethernet@d0070000 { mdio {
status = "okay"; phy0: ethernet-phy@0 {
phy = <&phy0>; reg = <16>;
phy-mode = "rgmii-id"; };
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@d0030000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
ethernet@d0034000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};
spi0: spi@d0010600 { phy1: ethernet-phy@1 {
status = "okay"; reg = <17>;
};
spi-flash@0 { phy2: ethernet-phy@2 {
#address-cells = <1>; reg = <18>;
#size-cells = <1>; };
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
devbus-bootcs@d0010400 { phy3: ethernet-phy@3 {
status = "okay"; reg = <19>;
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ };
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
}; };
};
pcie-controller { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};
/* spi0: spi@10600 {
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
}; };
pcie@9,0 {
/* Port 2, Lane 0 */ devbus-bootcs@10400 {
status = "okay"; status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
}; };
pcie@10,0 {
/* Port 3, Lane 0 */ pcie-controller {
status = "okay"; status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View file @ 38f56f33
...@@ -25,159 +25,161 @@ aliases { ...@@ -25,159 +25,161 @@ aliases {
}; };
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu@0 { cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "marvell,sheeva-v7"; compatible = "marvell,sheeva-v7";
reg = <0>; reg = <0>;
clocks = <&cpuclk 0>; clocks = <&cpuclk 0>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
};
soc {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
reg = <0xd0018000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
}; };
gpio1: gpio@d0018140 { cpu@1 {
compatible = "marvell,orion-gpio"; device_type = "cpu";
reg = <0xd0018140 0x40>; compatible = "marvell,sheeva-v7";
ngpios = <17>; reg = <1>;
gpio-controller; clocks = <&cpuclk 1>;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
}; };
};
/* soc {
* MV78230 has 2 PCIe units Gen2.0: One unit can be internal-regs {
* configured as x4 or quad x1 lanes. One unit is pinctrl {
* x4/x1. compatible = "marvell,mv78230-pinctrl";
*/ reg = <0x18000 0x38>;
pcie-controller {
compatible = "marvell,armada-xp-pcie"; sdio_pins: sdio-pins {
status = "disabled"; marvell,pins = "mpp30", "mpp31", "mpp32",
device_type = "pci"; "mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
#address-cells = <3>; };
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
}; };
pcie@2,0 { gpio0: gpio@18100 {
device_type = "pci"; compatible = "marvell,orion-gpio";
assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; reg = <0x18100 0x40>;
reg = <0x1000 0 0 0 0>; ngpios = <32>;
#address-cells = <3>; gpio-controller;
#size-cells = <2>; #gpio-cells = <2>;
#interrupt-cells = <1>; interrupt-controller;
ranges; #interrupts-cells = <2>;
interrupt-map-mask = <0 0 0 0>; interrupts = <82>, <83>, <84>, <85>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
}; };
pcie@3,0 { gpio1: gpio@18140 {
device_type = "pci"; compatible = "marvell,orion-gpio";
assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; reg = <0x18140 0x40>;
reg = <0x1800 0 0 0 0>; ngpios = <17>;
#address-cells = <3>; gpio-controller;
#size-cells = <2>; #gpio-cells = <2>;
#interrupt-cells = <1>; interrupt-controller;
ranges; #interrupts-cells = <2>;
interrupt-map-mask = <0 0 0 0>; interrupts = <87>, <88>, <89>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
}; };
pcie@4,0 { /*
device_type = "pci"; * MV78230 has 2 PCIe units Gen2.0: One unit can be
assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; * configured as x4 or quad x1 lanes. One unit is
reg = <0x2000 0 0 0 0>; * x4/x1.
#address-cells = <3>; */
#size-cells = <2>; pcie-controller {
#interrupt-cells = <1>; compatible = "marvell,armada-xp-pcie";
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled"; status = "disabled";
};
pcie@9,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
reg = <0x4800 0 0 0 0>; #address-cells = <3>;
#address-cells = <3>; #size-cells = <2>;
#size-cells = <2>;
#interrupt-cells = <1>; bus-range = <0x00 0xff>;
ranges;
interrupt-map-mask = <0 0 0 0>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
interrupt-map = <0 0 0 0 &mpic 99>; 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
marvell,pcie-port = <2>; 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
marvell,pcie-lane = <0>; 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
clocks = <&gateclk 26>; 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
status = "disabled"; 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View file @ 38f56f33
...@@ -26,196 +26,198 @@ aliases { ...@@ -26,196 +26,198 @@ aliases {
}; };
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu@0 { cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "marvell,sheeva-v7"; compatible = "marvell,sheeva-v7";
reg = <0>; reg = <0>;
clocks = <&cpuclk 0>; clocks = <&cpuclk 0>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "marvell,sheeva-v7"; compatible = "marvell,sheeva-v7";
reg = <1>; reg = <1>;
clocks = <&cpuclk 1>; clocks = <&cpuclk 1>;
}; };
}; };
soc { soc {
pinctrl { internal-regs {
compatible = "marvell,mv78260-pinctrl"; pinctrl {
reg = <0xd0018000 0x38>; compatible = "marvell,mv78260-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32", sdio_pins: sdio-pins {
"mpp33", "mpp34", "mpp35"; marvell,pins = "mpp30", "mpp31", "mpp32",
marvell,function = "sd0"; "mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
}; };
};
gpio0: gpio@d0018100 { gpio0: gpio@18100 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>; reg = <0x18100 0x40>;
ngpios = <32>; ngpios = <32>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>; interrupts = <82>, <83>, <84>, <85>;
}; };
gpio1: gpio@d0018140 { gpio1: gpio@18140 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>; reg = <0x18140 0x40>;
ngpios = <32>; ngpios = <32>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>; interrupts = <87>, <88>, <89>, <90>;
}; };
gpio2: gpio@d0018180 { gpio2: gpio@18180 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>; reg = <0x18180 0x40>;
ngpios = <3>; ngpios = <3>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <91>; interrupts = <91>;
}; };
ethernet@d0034000 { ethernet@34000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0xd0034000 0x2500>; reg = <0x34000 0x2500>;
interrupts = <14>; interrupts = <14>;
clocks = <&gateclk 1>; clocks = <&gateclk 1>;
status = "disabled"; status = "disabled";
};
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
}; };
pcie@3,0 { /*
device_type = "pci"; * MV78260 has 3 PCIe units Gen2.0: Two units can be
assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; * configured as x4 or quad x1 lanes. One unit is
reg = <0x1800 0 0 0 0>; * x4/x1.
#address-cells = <3>; */
#size-cells = <2>; pcie-controller {
#interrupt-cells = <1>; compatible = "marvell,armada-xp-pcie";
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled"; status = "disabled";
};
pcie@4,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 { bus-range = <0x00 0xff>;
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
reg = <0x5000 0 0 0 0>; 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
#address-cells = <3>; 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
#size-cells = <2>; 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
#interrupt-cells = <1>; 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
ranges; 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
interrupt-map-mask = <0 0 0 0>; 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
interrupt-map = <0 0 0 0 &mpic 103>; 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
marvell,pcie-port = <3>; 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>; pcie@1,0 {
status = "disabled"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View file @ 38f56f33
This diff is collapsed.
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file @ 38f56f33
...@@ -23,158 +23,160 @@ chosen { ...@@ -23,158 +23,160 @@ chosen {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0xC0000000>; /* 3 GB */ reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
}; };
soc { soc {
serial@d0012000 { internal-regs {
clock-frequency = <250000000>; serial@12000 {
status = "okay"; clock-frequency = <250000000>;
}; status = "okay";
serial@d0012100 {
clock-frequency = <250000000>;
status = "okay";
};
pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
marvell,function = "gpio";
}; };
}; serial@12100 {
leds { clock-frequency = <250000000>;
compatible = "gpio-leds"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
}; };
pinctrl {
yellow_led { led_pins: led-pins-0 {
label = "yellow_led"; marvell,pins = "mpp49", "mpp51", "mpp53";
gpios = <&gpio1 19 1>; marvell,function = "gpio";
default-state = "off"; };
}; };
leds {
green_led { compatible = "gpio-leds";
label = "green_led"; pinctrl-names = "default";
gpios = <&gpio1 21 1>; pinctrl-0 = <&led_pins>;
default-state = "off";
linux,default-trigger = "heartbeat"; red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
};
yellow_led {
label = "yellow_led";
gpios = <&gpio1 19 1>;
default-state = "off";
};
green_led {
label = "green_led";
gpios = <&gpio1 21 1>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
}; };
};
gpio_keys { gpio_keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
button@1 { button@1 {
label = "Init Button"; label = "Init Button";
linux,code = <116>; linux,code = <116>;
gpios = <&gpio1 28 0>; gpios = <&gpio1 28 0>;
};
}; };
};
mdio { mdio {
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
reg = <1>; reg = <1>;
}; };
phy2: ethernet-phy@2 { phy2: ethernet-phy@2 {
reg = <2>; reg = <2>;
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
reg = <3>; reg = <3>;
};
}; };
};
ethernet@d0070000 { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>; phy = <&phy0>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@d0074000 { ethernet@74000 {
status = "okay"; status = "okay";
phy = <&phy1>; phy = <&phy1>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@d0030000 { ethernet@30000 {
status = "okay"; status = "okay";
phy = <&phy2>; phy = <&phy2>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@d0034000 { ethernet@34000 {
status = "okay"; status = "okay";
phy = <&phy3>; phy = <&phy3>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
i2c@d0011000 { i2c@11000 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
i2c@d0011100 { i2c@11100 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
s35390a: s35390a@30 { s35390a: s35390a@30 {
compatible = "s35390a"; compatible = "s35390a";
reg = <0x30>; reg = <0x30>;
};
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
}; };
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
devbus-bootcs@d0010400 { devbus-bootcs@10400 {
status = "okay"; status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */ /* Device Bus parameters are required */
/* Read parameters */ /* Read parameters */
devbus,bus-width = <8>; devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>; devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>; devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>; devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>; devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>; devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>; devbus,rd-hold-ps = <0>;
/* Write parameters */ /* Write parameters */
devbus,sync-enable = <0>; devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>; devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>; devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>; devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */ /* NOR 128 MiB */
nor@0 { nor@0 {
compatible = "cfi-flash"; compatible = "cfi-flash";
reg = <0 0x8000000>; reg = <0 0x8000000>;
bank-width = <2>; bank-width = <2>;
};
}; };
};
pcie-controller { pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp.dtsi
View file @ 38f56f33
...@@ -22,140 +22,140 @@ / { ...@@ -22,140 +22,140 @@ / {
model = "Marvell Armada XP family SoC"; model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,armadaxp", "marvell,armada-370-xp";
L2: l2-cache { soc {
compatible = "marvell,aurora-system-cache"; internal-regs {
reg = <0xd0008000 0x1000>; L2: l2-cache {
cache-id-part = <0x100>; compatible = "marvell,aurora-system-cache";
wt-override; reg = <0x08000 0x1000>;
}; cache-id-part = <0x100>;
wt-override;
};
mpic: interrupt-controller@d0020000 { mpic: interrupt-controller@20000 {
reg = <0xd0020a00 0x2d0>, reg = <0x20a00 0x2d0>, <0x21070 0x58>;
<0xd0021070 0x58>; };
};
armada-370-xp-pmsu@d0022000 { armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu"; compatible = "marvell,armada-370-xp-pmsu";
reg = <0xd0022100 0x430>, reg = <0x22100 0x430>, <0x20800 0x20>;
<0xd0020800 0x20>; };
};
soc { serial@12200 {
serial@d0012200 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0xd0012200 0x100>; reg = <0x12200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <43>; interrupts = <43>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
serial@d0012300 { serial@12300 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0xd0012300 0x100>; reg = <0x12300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <44>; interrupts = <44>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
timer@d0020300 { timer@20300 {
marvell,timer-25Mhz; marvell,timer-25Mhz;
}; };
coreclk: mvebu-sar@d0018230 { coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-xp-core-clock"; compatible = "marvell,armada-xp-core-clock";
reg = <0xd0018230 0x08>; reg = <0x18230 0x08>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
cpuclk: clock-complex@d0018700 { cpuclk: clock-complex@18700 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock"; compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xA0>; reg = <0x18700 0xA0>;
clocks = <&coreclk 1>; clocks = <&coreclk 1>;
}; };
gateclk: clock-gating-control@d0018220 { gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-xp-gating-clock"; compatible = "marvell,armada-xp-gating-clock";
reg = <0xd0018220 0x4>; reg = <0x18220 0x4>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
system-controller@d0018200 { system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller"; compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x500>; reg = <0x18200 0x500>;
}; };
ethernet@d0030000 { ethernet@30000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0xd0030000 0x2500>; reg = <0x30000 0x2500>;
interrupts = <12>; interrupts = <12>;
clocks = <&gateclk 2>; clocks = <&gateclk 2>;
status = "disabled"; status = "disabled";
};
xor@d0060900 {
compatible = "marvell,orion-xor";
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor10 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
}; };
};
xor@d00f0900 { xor@60900 {
compatible = "marvell,orion-xor"; compatible = "marvell,orion-xor";
reg = <0xd00F0900 0x100 reg = <0x60900 0x100
0xd00F0B00 0x100>; 0x60b00 0x100>;
clocks = <&gateclk 28>; clocks = <&gateclk 22>;
status = "okay"; status = "okay";
xor00 { xor10 {
interrupts = <94>; interrupts = <51>;
dmacap,memcpy; dmacap,memcpy;
dmacap,xor; dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
}; };
xor01 {
interrupts = <95>; xor@f0900 {
dmacap,memcpy; compatible = "marvell,orion-xor";
dmacap,xor; reg = <0xF0900 0x100
dmacap,memset; 0xF0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor00 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
}; };
};
usb@d0050000 { usb@50000 {
clocks = <&gateclk 18>; clocks = <&gateclk 18>;
}; };
usb@d0051000 { usb@51000 {
clocks = <&gateclk 19>; clocks = <&gateclk 19>;
}; };
usb@d0052000 { usb@52000 {
compatible = "marvell,orion-ehci"; compatible = "marvell,orion-ehci";
reg = <0xd0052000 0x500>; reg = <0x52000 0x500>;
interrupts = <47>; interrupts = <47>;
clocks = <&gateclk 20>; clocks = <&gateclk 20>;
status = "disabled"; status = "disabled";
}; };
thermal@d00182b0 { thermal@182b0 {
compatible = "marvell,armadaxp-thermal"; compatible = "marvell,armadaxp-thermal";
reg = <0xd00182b0 0x4 reg = <0x182b0 0x4
0xd00184d0 0x4>; 0x184d0 0x4>;
status = "okay"; status = "okay";
};
}; };
}; };
}; };
arch/arm/boot/dts/cros5250-common.dtsi
View file @ 38f56f33
...@@ -19,11 +19,19 @@ memory { ...@@ -19,11 +19,19 @@ memory {
chosen { chosen {
}; };
pinctrl@11400000 {
/*
* Disabled pullups since external part has its own pullups and
* double-pulling gets us out of spec in some cases.
*/
i2c2_bus: i2c2-bus {
samsung,pin-pud = <0>;
};
};
i2c@12C60000 { i2c@12C60000 {
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>; samsung,i2c-max-bus-freq = <378000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
max77686@09 { max77686@09 {
compatible = "maxim,max77686"; compatible = "maxim,max77686";
...@@ -167,21 +175,12 @@ buck8_reg: BUCK8 { ...@@ -167,21 +175,12 @@ buck8_reg: BUCK8 {
i2c@12C70000 { i2c@12C70000 {
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>; samsung,i2c-max-bus-freq = <378000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
}; };
i2c@12C80000 { i2c@12C80000 {
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>; samsung,i2c-max-bus-freq = <66000>;
/*
* Disabled pullups since external part has its own pullups and
* double-pulling gets us out of spec in some cases.
*/
gpios = <&gpa0 6 3 0 0>,
<&gpa0 7 3 0 0>;
hdmiddc@50 { hdmiddc@50 {
compatible = "samsung,exynos5-hdmiddc"; compatible = "samsung,exynos5-hdmiddc";
reg = <0x50>; reg = <0x50>;
...@@ -191,19 +190,16 @@ hdmiddc@50 { ...@@ -191,19 +190,16 @@ hdmiddc@50 {
i2c@12C90000 { i2c@12C90000 {
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>; samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpa1 2 3 3 0>,
<&gpa1 3 3 3 0>;
}; };
i2c@12CA0000 { i2c@12CA0000 {
status = "disabled"; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
}; };
i2c@12CB0000 { i2c@12CB0000 {
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>; samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpa2 2 3 3 0>,
<&gpa2 3 3 3 0>;
}; };
i2c@12CC0000 { i2c@12CC0000 {
...@@ -213,8 +209,6 @@ i2c@12CC0000 { ...@@ -213,8 +209,6 @@ i2c@12CC0000 {
i2c@12CD0000 { i2c@12CD0000 {
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>; samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpb2 2 3 3 0>,
<&gpb2 3 3 3 0>;
}; };
i2c@12CE0000 { i2c@12CE0000 {
...@@ -236,15 +230,12 @@ dwmmc0@12200000 { ...@@ -236,15 +230,12 @@ dwmmc0@12200000 {
samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
slot@0 { slot@0 {
reg = <0>; reg = <0>;
bus-width = <8>; bus-width = <8>;
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
}; };
}; };
...@@ -260,15 +251,13 @@ dwmmc2@12220000 { ...@@ -260,15 +251,13 @@ dwmmc2@12220000 {
samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 { slot@0 {
reg = <0>; reg = <0>;
bus-width = <4>; bus-width = <4>;
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; wp-gpios = <&gpc2 1 0>;
wp-gpios = <&gpc2 1 0 0 3>;
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
}; };
}; };
...@@ -281,11 +270,11 @@ dwmmc3@12230000 { ...@@ -281,11 +270,11 @@ dwmmc3@12230000 {
samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
/* See board-specific dts files for pin setup */
slot@0 { slot@0 {
reg = <0>; reg = <0>;
bus-width = <4>; bus-width = <4>;
/* See board-specific dts files for GPIOs */
}; };
}; };
...@@ -294,9 +283,6 @@ spi_0: spi@12d20000 { ...@@ -294,9 +283,6 @@ spi_0: spi@12d20000 {
}; };
spi_1: spi@12d30000 { spi_1: spi@12d30000 {
gpios = <&gpa2 4 2 3 0>,
<&gpa2 6 2 3 0>,
<&gpa2 7 2 3 0>;
samsung,spi-src-clk = <0>; samsung,spi-src-clk = <0>;
num-cs = <1>; num-cs = <1>;
}; };
...@@ -306,7 +292,7 @@ spi_2: spi@12d40000 { ...@@ -306,7 +292,7 @@ spi_2: spi@12d40000 {
}; };
hdmi { hdmi {
hpd-gpio = <&gpx3 7 0xf 1 3>; hpd-gpio = <&gpx3 7 0>;
}; };
gpio-keys { gpio-keys {
...@@ -314,7 +300,7 @@ gpio-keys { ...@@ -314,7 +300,7 @@ gpio-keys {
power { power {
label = "Power"; label = "Power";
gpios = <&gpx1 3 0 0x10000 0>; gpios = <&gpx1 3 1>;
linux,code = <116>; /* KEY_POWER */ linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup; gpio-key,wakeup;
}; };
......
arch/arm/boot/dts/da850-evm.dts
View file @ 38f56f33
...@@ -50,6 +50,46 @@ mmc0: mmc@1c40000 { ...@@ -50,6 +50,46 @@ mmc0: mmc@1c40000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>; pinctrl-0 = <&mmc0_pins>;
}; };
spi1: spi@1f0e000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
spi-max-frequency = <30000000>;
reg = <0>;
partition@0 {
label = "U-Boot-SPL";
reg = <0x00000000 0x00010000>;
read-only;
};
partition@1 {
label = "U-Boot";
reg = <0x00010000 0x00080000>;
read-only;
};
partition@2 {
label = "U-Boot-Env";
reg = <0x00090000 0x00010000>;
read-only;
};
partition@3 {
label = "Kernel";
reg = <0x000a0000 0x00280000>;
};
partition@4 {
label = "Filesystem";
reg = <0x00320000 0x00400000>;
};
partition@5 {
label = "MAC-Address";
reg = <0x007f0000 0x00010000>;
read-only;
};
};
};
}; };
nand_cs3@62000000 { nand_cs3@62000000 {
status = "okay"; status = "okay";
......
arch/arm/boot/dts/da850.dtsi
View file @ 38f56f33
...@@ -71,6 +71,60 @@ mmc0_pins: pinmux_mmc_pins { ...@@ -71,6 +71,60 @@ mmc0_pins: pinmux_mmc_pins {
0x28 0x00222222 0x00ffffff 0x28 0x00222222 0x00ffffff
>; >;
}; };
ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
pinctrl-single,bits = <
/* EPWM0A */
0xc 0x00000002 0x0000000f
>;
};
ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
pinctrl-single,bits = <
/* EPWM0B */
0xc 0x00000020 0x000000f0
>;
};
ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
pinctrl-single,bits = <
/* EPWM1A */
0x14 0x00000002 0x0000000f
>;
};
ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
pinctrl-single,bits = <
/* EPWM1B */
0x14 0x00000020 0x000000f0
>;
};
ecap0_pins: pinmux_ecap0_pins {
pinctrl-single,bits = <
/* ECAP0_APWM0 */
0x8 0x20000000 0xf0000000
>;
};
ecap1_pins: pinmux_ecap1_pins {
pinctrl-single,bits = <
/* ECAP1_APWM1 */
0x4 0x40000000 0xf0000000
>;
};
ecap2_pins: pinmux_ecap2_pins {
pinctrl-single,bits = <
/* ECAP2_APWM2 */
0x4 0x00000004 0x0000000f
>;
};
spi1_pins: pinmux_spi_pins {
pinctrl-single,bits = <
/* SIMO, SOMI, CLK */
0x14 0x00110100 0x00ff0f00
>;
};
spi1_cs0_pin: pinmux_spi1_cs0 {
pinctrl-single,bits = <
/* CS0 */
0x14 0x00000010 0x000000f0
>;
};
}; };
serial0: serial@1c42000 { serial0: serial@1c42000 {
compatible = "ns16550a"; compatible = "ns16550a";
...@@ -122,6 +176,46 @@ mmc0: mmc@1c40000 { ...@@ -122,6 +176,46 @@ mmc0: mmc@1c40000 {
interrupts = <16>; interrupts = <16>;
status = "disabled"; status = "disabled";
}; };
ehrpwm0: ehrpwm@01f00000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
status = "disabled";
};
ehrpwm1: ehrpwm@01f02000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
status = "disabled";
};
ecap0: ecap@01f06000 {
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
status = "disabled";
};
ecap1: ecap@01f07000 {
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x307000 0x80>;
status = "disabled";
};
ecap2: ecap@01f08000 {
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x308000 0x80>;
status = "disabled";
};
spi1: spi@1f0e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,da830-spi";
reg = <0x30e000 0x1000>;
num-cs = <4>;
ti,davinci-spi-intr-line = <1>;
interrupts = <56>;
status = "disabled";
};
}; };
nand_cs3@62000000 { nand_cs3@62000000 {
compatible = "ti,davinci-nand"; compatible = "ti,davinci-nand";
......
arch/arm/boot/dts/exynos4.dtsi
View file @ 38f56f33
...@@ -38,6 +38,11 @@ aliases { ...@@ -38,6 +38,11 @@ aliases {
i2c7 = &i2c_7; i2c7 = &i2c_7;
}; };
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
pd_mfc: mfc-power-domain@10023C40 { pd_mfc: mfc-power-domain@10023C40 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>; reg = <0x10023C40 0x20>;
...@@ -82,6 +87,11 @@ combiner:interrupt-controller@10440000 { ...@@ -82,6 +87,11 @@ combiner:interrupt-controller@10440000 {
reg = <0x10440000 0x1000>; reg = <0x10440000 0x1000>;
}; };
sys_reg: sysreg {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};
watchdog@10060000 { watchdog@10060000 {
compatible = "samsung,s3c2410-wdt"; compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>; reg = <0x10060000 0x100>;
...@@ -197,6 +207,8 @@ i2c_0: i2c@13860000 { ...@@ -197,6 +207,8 @@ i2c_0: i2c@13860000 {
interrupts = <0 58 0>; interrupts = <0 58 0>;
clocks = <&clock 317>; clocks = <&clock 317>;
clock-names = "i2c"; clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
status = "disabled"; status = "disabled";
}; };
...@@ -208,6 +220,8 @@ i2c_1: i2c@13870000 { ...@@ -208,6 +220,8 @@ i2c_1: i2c@13870000 {
interrupts = <0 59 0>; interrupts = <0 59 0>;
clocks = <&clock 318>; clocks = <&clock 318>;
clock-names = "i2c"; clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
status = "disabled"; status = "disabled";
}; };
...@@ -287,6 +301,8 @@ spi_0: spi@13920000 { ...@@ -287,6 +301,8 @@ spi_0: spi@13920000 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 327>, <&clock 159>; clocks = <&clock 327>, <&clock 159>;
clock-names = "spi", "spi_busclk0"; clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled"; status = "disabled";
}; };
...@@ -300,6 +316,8 @@ spi_1: spi@13930000 { ...@@ -300,6 +316,8 @@ spi_1: spi@13930000 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 328>, <&clock 160>; clocks = <&clock 328>, <&clock 160>;
clock-names = "spi", "spi_busclk0"; clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled"; status = "disabled";
}; };
...@@ -313,6 +331,8 @@ spi_2: spi@13940000 { ...@@ -313,6 +331,8 @@ spi_2: spi@13940000 {
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 329>, <&clock 161>; clocks = <&clock 329>, <&clock 161>;
clock-names = "spi", "spi_busclk0"; clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
status = "disabled"; status = "disabled";
}; };
...@@ -356,4 +376,16 @@ mdma1: mdma@12850000 { ...@@ -356,4 +376,16 @@ mdma1: mdma@12850000 {
#dma-requests = <1>; #dma-requests = <1>;
}; };
}; };
fimd: fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock 140>, <&clock 283>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
status = "disabled";
};
}; };
arch/arm/boot/dts/exynos4210-origen.dts
View file @ 38f56f33
...@@ -57,6 +57,10 @@ sdhci@12510000 { ...@@ -57,6 +57,10 @@ sdhci@12510000 {
status = "okay"; status = "okay";
}; };
g2d@12800000 {
status = "okay";
};
codec@13400000 { codec@13400000 {
samsung,mfc-r = <0x43000000 0x800000>; samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>; samsung,mfc-l = <0x51000000 0x800000>;
......
arch/arm/boot/dts/exynos4210-smdkv310.dts
View file @ 38f56f33
...@@ -30,16 +30,13 @@ chosen { ...@@ -30,16 +30,13 @@ chosen {
}; };
sdhci@12530000 { sdhci@12530000 {
samsung,sdhci-bus-width = <4>; bus-width = <4>;
linux,mmc_cap_4_bit_data; pinctrl-names = "default";
samsung,sdhci-cd-internal; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
gpio-cd = <&gpk2 2 2 3 3>; status = "okay";
gpios = <&gpk2 0 2 0 3>, };
<&gpk2 1 2 0 3>,
<&gpk2 3 2 3 3>, g2d@12800000 {
<&gpk2 4 2 3 3>,
<&gpk2 5 2 3 3>,
<&gpk2 6 2 3 3>;
status = "okay"; status = "okay";
}; };
...@@ -65,25 +62,32 @@ serial@13830000 { ...@@ -65,25 +62,32 @@ serial@13830000 {
status = "okay"; status = "okay";
}; };
pinctrl@11000000 {
keypad_rows: keypad-rows {
samsung,pins = "gpx2-0", "gpx2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
keypad_cols: keypad-cols {
samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
"gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
keypad@100A0000 { keypad@100A0000 {
samsung,keypad-num-rows = <2>; samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>; samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat; linux,keypad-no-autorepeat;
linux,keypad-wakeup; linux,keypad-wakeup;
pinctrl-names = "default";
pinctrl-0 = <&keypad_rows &keypad_cols>;
status = "okay"; status = "okay";
row-gpios = <&gpx2 0 3 3 0>,
<&gpx2 1 3 3 0>;
col-gpios = <&gpx1 0 3 0 0>,
<&gpx1 1 3 0 0>,
<&gpx1 2 3 0 0>,
<&gpx1 3 3 0 0>,
<&gpx1 4 3 0 0>,
<&gpx1 5 3 0 0>,
<&gpx1 6 3 0 0>,
<&gpx1 7 3 0 0>;
key_1 { key_1 {
keypad,row = <0>; keypad,row = <0>;
keypad,column = <3>; keypad,column = <3>;
...@@ -149,9 +153,7 @@ i2c@13860000 { ...@@ -149,9 +153,7 @@ i2c@13860000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
samsung,i2c-sda-delay = <100>; samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>; samsung,i2c-max-bus-freq = <100000>;
gpios = <&gpd1 0 2 3 0>,
<&gpd1 1 2 3 0>;
status = "okay"; status = "okay";
eeprom@50 { eeprom@50 {
...@@ -166,9 +168,6 @@ eeprom@52 { ...@@ -166,9 +168,6 @@ eeprom@52 {
}; };
spi_2: spi@13940000 { spi_2: spi@13940000 {
gpios = <&gpc1 1 5 3 0>,
<&gpc1 3 5 3 0>,
<&gpc1 4 5 3 0>;
status = "okay"; status = "okay";
w25x80@0 { w25x80@0 {
...@@ -179,7 +178,7 @@ w25x80@0 { ...@@ -179,7 +178,7 @@ w25x80@0 {
spi-max-frequency = <1000000>; spi-max-frequency = <1000000>;
controller-data { controller-data {
cs-gpio = <&gpc1 2 1 0 3>; cs-gpio = <&gpc1 2 0>;
samsung,spi-feedback-delay = <0>; samsung,spi-feedback-delay = <0>;
}; };
......
arch/arm/boot/dts/exynos4210.dtsi
View file @ 38f56f33
...@@ -112,4 +112,11 @@ tmu@100C0000 { ...@@ -112,4 +112,11 @@ tmu@100C0000 {
reg = <0x100C0000 0x100>; reg = <0x100C0000 0x100>;
interrupts = <2 4>; interrupts = <2 4>;
}; };
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
};
}; };
arch/arm/boot/dts/exynos4412-origen.dts
View file @ 38f56f33
...@@ -72,6 +72,27 @@ codec@13400000 { ...@@ -72,6 +72,27 @@ codec@13400000 {
status = "okay"; status = "okay";
}; };
fimd@11c00000 {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
};
display-timings {
native-mode = <&timing0>;
timing0: timing {
clock-frequency = <50000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <64>;
hback-porch = <16>;
hsync-len = <48>;
vback-porch = <64>;
vfront-porch = <16>;
vsync-len = <3>;
};
};
serial@13800000 { serial@13800000 {
status = "okay"; status = "okay";
}; };
......
arch/arm/boot/dts/exynos4412-smdk4412.dts
View file @ 38f56f33
...@@ -27,6 +27,14 @@ chosen { ...@@ -27,6 +27,14 @@ chosen {
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
}; };
g2d@10800000 {
status = "okay";
};
g2d@10800000 {
status = "okay";
};
sdhci@12530000 { sdhci@12530000 {
bus-width = <4>; bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
......
arch/arm/boot/dts/exynos4412.dtsi
View file @ 38f56f33
...@@ -51,4 +51,12 @@ mct_map: mct-map { ...@@ -51,4 +51,12 @@ mct_map: mct-map {
<0x7 0 &gic 1 12 0>; <0x7 0 &gic 1 12 0>;
}; };
}; };
mshc@12550000 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
};
}; };
arch/arm/boot/dts/exynos4x12.dtsi
View file @ 38f56f33
...@@ -72,4 +72,11 @@ pinctrl_3: pinctrl@106E0000 { ...@@ -72,4 +72,11 @@ pinctrl_3: pinctrl@106E0000 {
reg = <0x106E0000 0x1000>; reg = <0x106E0000 0x1000>;
interrupts = <0 72 0>; interrupts = <0 72 0>;
}; };
g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
};
}; };
arch/arm/boot/dts/exynos5250-arndale.dts
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/*
* SAMSUNG SD5v1 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "exynos5440.dtsi"
/ {
model = "SAMSUNG SD5v1 board based on EXYNOS5440";
compatible = "samsung,sd5v1", "samsung,exynos5440";
chosen {
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
};
fixed-rate-clocks {
xtal {
compatible = "samsung,clock-xtal";
clock-frequency = <50000000>;
};
};
gmac: ethernet@00230000 {
fixed_phy;
phy_addr = <1>;
};
spi {
status = "disabled";
};
};
arch/arm/boot/dts/exynos5440-ssdk5440.dts
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...@@ -29,6 +29,7 @@ ssp0: ssp@80010000 { ...@@ -29,6 +29,7 @@ ssp0: ssp@80010000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
bus-width = <4>; bus-width = <4>;
broken-cd;
status = "okay"; status = "okay";
}; };
......
arch/arm/boot/dts/imx23.dtsi
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