Commit 3ba9adf0 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski

Merge tag 'samsung-dt-exynos-srom-fixup-4.7' into for-v4.7/drivers-memory-exynos-srom

DeviceTree changes for new SROM controller driver reached mainline
some time ago, before the driver was accepted (due to very late
comments). However, after these late comments, the driver expects
different bindings so we need to fix the DTS.
parents f55532a0 4d7820b0
...@@ -77,8 +77,8 @@ chipid@10000000 { ...@@ -77,8 +77,8 @@ chipid@10000000 {
reg = <0x10000000 0x100>; reg = <0x10000000 0x100>;
}; };
sromc@12570000 { memory-controller@12570000 {
compatible = "samsung,exynos-srom"; compatible = "samsung,exynos4210-srom";
reg = <0x12570000 0x14>; reg = <0x12570000 0x14>;
}; };
......
...@@ -31,8 +31,8 @@ chipid@10000000 { ...@@ -31,8 +31,8 @@ chipid@10000000 {
reg = <0x10000000 0x100>; reg = <0x10000000 0x100>;
}; };
sromc@12250000 { memory-controller@12250000 {
compatible = "samsung,exynos-srom"; compatible = "samsung,exynos4210-srom";
reg = <0x12250000 0x14>; reg = <0x12250000 0x14>;
}; };
......
...@@ -97,7 +97,7 @@ ethernet@3,0 { ...@@ -97,7 +97,7 @@ ethernet@3,0 {
smsc,irq-push-pull; smsc,irq-push-pull;
smsc,force-internal-phy; smsc,force-internal-phy;
samsung,srom-page-mode = <1>; samsung,srom-page-mode;
samsung,srom-timing = <9 12 1 9 1 1>; samsung,srom-timing = <9 12 1 9 1 1>;
}; };
}; };
......
...@@ -102,8 +102,8 @@ chipid@10000000 { ...@@ -102,8 +102,8 @@ chipid@10000000 {
reg = <0x10000000 0x100>; reg = <0x10000000 0x100>;
}; };
sromc: sromc@12250000 { sromc: memory-controller@12250000 {
compatible = "samsung,exynos-srom"; compatible = "samsung,exynos4210-srom";
reg = <0x12250000 0x14>; reg = <0x12250000 0x14>;
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
......
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