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Commit 3be5262e authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
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drm/amd/display: Rename more dc_surface stuff to plane_state 

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0971c40e
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Showing with 658 additions and 657 deletions
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View file @ 3be5262e
......@@ -196,7 +196,7 @@ struct dc_stream;
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *surface;
struct dc_plane_state *dc_state;
};
struct dm_crtc_state {
......
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
View file @ 3be5262e
......@@ -2594,15 +2594,15 @@ static void populate_initial_data(
if (!pipe[i].stream || !pipe[i].bottom_pipe)
continue;
ASSERT(pipe[i].surface);
ASSERT(pipe[i].plane_state);
if (num_displays == 0) {
if (!pipe[i].surface->visible)
if (!pipe[i].plane_state->visible)
data->d0_underlay_mode = bw_def_underlay_only;
else
data->d0_underlay_mode = bw_def_blend;
} else {
if (!pipe[i].surface->visible)
if (!pipe[i].plane_state->visible)
data->d1_underlay_mode = bw_def_underlay_only;
else
data->d1_underlay_mode = bw_def_blend;
......@@ -2620,7 +2620,7 @@ static void populate_initial_data(
data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps);
data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value);
data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value);
switch (pipe[i].surface->rotation) {
switch (pipe[i].plane_state->rotation) {
case ROTATION_ANGLE_0:
data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
break;
......@@ -2636,7 +2636,7 @@ static void populate_initial_data(
default:
break;
}
switch (pipe[i].surface->format) {
switch (pipe[i].plane_state->format) {
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
......@@ -2670,14 +2670,14 @@ static void populate_initial_data(
data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.height);
data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.width);
data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
pipe[i].bottom_pipe->surface->plane_size.grph.surface_pitch);
pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);
data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.h_taps);
data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.v_taps);
data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
pipe[i].bottom_pipe->scl_data.ratios.horz.value);
data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
pipe[i].bottom_pipe->scl_data.ratios.vert.value);
switch (pipe[i].bottom_pipe->surface->rotation) {
switch (pipe[i].bottom_pipe->plane_state->rotation) {
case ROTATION_ANGLE_0:
data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0);
break;
......@@ -2710,7 +2710,7 @@ static void populate_initial_data(
data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
if (pipe[i].surface) {
if (pipe[i].plane_state) {
data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);
data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height);
......@@ -2718,7 +2718,7 @@ static void populate_initial_data(
data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps);
data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value);
data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value);
switch (pipe[i].surface->rotation) {
switch (pipe[i].plane_state->rotation) {
case ROTATION_ANGLE_0:
data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
break;
......@@ -2734,7 +2734,7 @@ static void populate_initial_data(
default:
break;
}
switch (pipe[i].surface->format) {
switch (pipe[i].plane_state->format) {
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
......
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
View file @ 3be5262e
......@@ -233,16 +233,16 @@ static void pipe_ctx_to_e2e_pipe_params (
struct _vcs_dpi_display_pipe_params_st *input)
{
input->src.is_hsplit = false;
if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface)
if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
input->src.is_hsplit = true;
else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface)
else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
input->src.is_hsplit = true;
input->src.dcc = pipe->surface->dcc.enable;
input->src.dcc = pipe->plane_state->dcc.enable;
input->src.dcc_rate = 1;
input->src.meta_pitch = pipe->surface->dcc.grph.meta_pitch;
input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch;
input->src.source_scan = dm_horz;
input->src.sw_mode = pipe->surface->tiling_info.gfx9.swizzle;
input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
input->src.viewport_width = pipe->scl_data.viewport.width;
input->src.viewport_height = pipe->scl_data.viewport.height;
......@@ -251,7 +251,7 @@ static void pipe_ctx_to_e2e_pipe_params (
input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
input->src.cur0_bpp = 32;
switch (pipe->surface->tiling_info.gfx9.swizzle) {
switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
/* for 4/8/16 high tiles */
case DC_SW_LINEAR:
input->src.is_display_sw = 1;
......@@ -299,7 +299,7 @@ static void pipe_ctx_to_e2e_pipe_params (
break;
}
switch (pipe->surface->rotation) {
switch (pipe->plane_state->rotation) {
case ROTATION_ANGLE_0:
case ROTATION_ANGLE_180:
input->src.source_scan = dm_horz;
......@@ -314,7 +314,7 @@ static void pipe_ctx_to_e2e_pipe_params (
}
/* TODO: Fix pixel format mappings */
switch (pipe->surface->format) {
switch (pipe->plane_state->format) {
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
input->src.source_format = dm_420_8;
......@@ -455,7 +455,7 @@ static void dcn_bw_calc_rq_dlg_ttu(
true,
true,
v->pte_enable == dcn_bw_yes,
pipe->surface->flip_immediate);
pipe->plane_state->flip_immediate);
}
static void dcn_dml_wm_override(
......@@ -478,7 +478,7 @@ static void dcn_dml_wm_override(
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (!pipe->stream || !pipe->surface)
if (!pipe->stream || !pipe->plane_state)
continue;
input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
......@@ -516,7 +516,7 @@ static void dcn_dml_wm_override(
for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (!pipe->stream || !pipe->surface)
if (!pipe->stream || !pipe->plane_state)
continue;
dml_rq_dlg_get_dlg_reg(dml,
......@@ -527,7 +527,7 @@ static void dcn_dml_wm_override(
true,
true,
v->pte_enable == dcn_bw_yes,
pipe->surface->flip_immediate);
pipe->plane_state->flip_immediate);
in_idx++;
}
dm_free(input);
......@@ -541,7 +541,7 @@ static void split_stream_across_pipes(
{
int pipe_idx = secondary_pipe->pipe_idx;
if (!primary_pipe->surface)
if (!primary_pipe->plane_state)
return;
*secondary_pipe = *primary_pipe;
......@@ -843,7 +843,7 @@ bool dcn_validate_bandwidth(
if (!pipe->stream)
continue;
/* skip all but first of split pipes */
if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
continue;
v->underscan_output[input_idx] = false; /* taken care of in recout already*/
......@@ -869,7 +869,7 @@ bool dcn_validate_bandwidth(
}
}
if (!pipe->surface){
if (!pipe->plane_state) {
v->dcc_enable[input_idx] = dcn_bw_yes;
v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
......@@ -889,8 +889,8 @@ bool dcn_validate_bandwidth(
v->viewport_width[input_idx] = pipe->scl_data.viewport.width;
v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width;
v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height;
if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) {
if (pipe->surface->rotation % 2 == 0) {
if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
if (pipe->plane_state->rotation % 2 == 0) {
int viewport_end = pipe->scl_data.viewport.width
+ pipe->scl_data.viewport.x;
int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width
......@@ -919,17 +919,17 @@ bool dcn_validate_bandwidth(
+ pipe->bottom_pipe->scl_data.recout.width;
}
v->dcc_enable[input_idx] = pipe->surface->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
pipe->surface->format);
pipe->plane_state->format);
v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
pipe->surface->tiling_info.gfx9.swizzle);
pipe->plane_state->tiling_info.gfx9.swizzle);
v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth);
v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps;
v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps;
v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c;
v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c;
v->source_scan[input_idx] = (pipe->surface->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
}
if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
......@@ -996,7 +996,7 @@ bool dcn_validate_bandwidth(
if (!pipe->stream)
continue;
/* skip all but first of split pipes */
if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
continue;
pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
......@@ -1024,7 +1024,7 @@ bool dcn_validate_bandwidth(
pipe->pipe_dlg_param.vblank_start = asic_blank_start;
pipe->pipe_dlg_param.vblank_end = asic_blank_end;
if (pipe->surface) {
if (pipe->plane_state) {
struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
if (v->dpp_per_plane[input_idx] == 2 ||
......@@ -1036,7 +1036,7 @@ bool dcn_validate_bandwidth(
TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
pipe->stream->timing.timing_3d_format ==
TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* update previously split pipe */
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
......@@ -1057,12 +1057,12 @@ bool dcn_validate_bandwidth(
}
dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe);
} else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* merge previously split pipe */
pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
if (hsplit_pipe->bottom_pipe)
hsplit_pipe->bottom_pipe->top_pipe = pipe;
hsplit_pipe->surface = NULL;
hsplit_pipe->plane_state = NULL;
hsplit_pipe->stream = NULL;
hsplit_pipe->top_pipe = NULL;
hsplit_pipe->bottom_pipe = NULL;
......
drivers/gpu/drm/amd/display/dc/core/dc.c
View file @ 3be5262e
This diff is collapsed.
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
View file @ 3be5262e
......@@ -38,7 +38,7 @@
void pre_surface_trace(
const struct dc *dc,
const struct dc_plane_state *const *surfaces,
const struct dc_plane_state *const *plane_states,
int surface_count)
{
int i;
......@@ -46,111 +46,111 @@ void pre_surface_trace(
struct dal_logger *logger = core_dc->ctx->logger;
for (i = 0; i < surface_count; i++) {
const struct dc_plane_state *surface = surfaces[i];
const struct dc_plane_state *plane_state = plane_states[i];
SURFACE_TRACE("Surface %d:\n", i);
SURFACE_TRACE("Planes %d:\n", i);
SURFACE_TRACE(
"surface->visible = %d;\n"
"surface->flip_immediate = %d;\n"
"surface->address.type = %d;\n"
"surface->address.grph.addr.quad_part = 0x%X;\n"
"surface->address.grph.meta_addr.quad_part = 0x%X;\n"
"surface->scaling_quality.h_taps = %d;\n"
"surface->scaling_quality.v_taps = %d;\n"
"surface->scaling_quality.h_taps_c = %d;\n"
"surface->scaling_quality.v_taps_c = %d;\n",
surface->visible,
surface->flip_immediate,
surface->address.type,
surface->address.grph.addr.quad_part,
surface->address.grph.meta_addr.quad_part,
surface->scaling_quality.h_taps,
surface->scaling_quality.v_taps,
surface->scaling_quality.h_taps_c,
surface->scaling_quality.v_taps_c);
"plane_state->visible = %d;\n"
"plane_state->flip_immediate = %d;\n"
"plane_state->address.type = %d;\n"
"plane_state->address.grph.addr.quad_part = 0x%X;\n"
"plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
"plane_state->scaling_quality.h_taps = %d;\n"
"plane_state->scaling_quality.v_taps = %d;\n"
"plane_state->scaling_quality.h_taps_c = %d;\n"
"plane_state->scaling_quality.v_taps_c = %d;\n",
plane_state->visible,
plane_state->flip_immediate,
plane_state->address.type,
plane_state->address.grph.addr.quad_part,
plane_state->address.grph.meta_addr.quad_part,
plane_state->scaling_quality.h_taps,
plane_state->scaling_quality.v_taps,
plane_state->scaling_quality.h_taps_c,
plane_state->scaling_quality.v_taps_c);
SURFACE_TRACE(
"surface->src_rect.x = %d;\n"
"surface->src_rect.y = %d;\n"
"surface->src_rect.width = %d;\n"
"surface->src_rect.height = %d;\n"
"surface->dst_rect.x = %d;\n"
"surface->dst_rect.y = %d;\n"
"surface->dst_rect.width = %d;\n"
"surface->dst_rect.height = %d;\n"
"surface->clip_rect.x = %d;\n"
"surface->clip_rect.y = %d;\n"
"surface->clip_rect.width = %d;\n"
"surface->clip_rect.height = %d;\n",
surface->src_rect.x,
surface->src_rect.y,
surface->src_rect.width,
surface->src_rect.height,
surface->dst_rect.x,
surface->dst_rect.y,
surface->dst_rect.width,
surface->dst_rect.height,
surface->clip_rect.x,
surface->clip_rect.y,
surface->clip_rect.width,
surface->clip_rect.height);
"plane_state->src_rect.x = %d;\n"
"plane_state->src_rect.y = %d;\n"
"plane_state->src_rect.width = %d;\n"
"plane_state->src_rect.height = %d;\n"
"plane_state->dst_rect.x = %d;\n"
"plane_state->dst_rect.y = %d;\n"
"plane_state->dst_rect.width = %d;\n"
"plane_state->dst_rect.height = %d;\n"
"plane_state->clip_rect.x = %d;\n"
"plane_state->clip_rect.y = %d;\n"
"plane_state->clip_rect.width = %d;\n"
"plane_state->clip_rect.height = %d;\n",
plane_state->src_rect.x,
plane_state->src_rect.y,
plane_state->src_rect.width,
plane_state->src_rect.height,
plane_state->dst_rect.x,
plane_state->dst_rect.y,
plane_state->dst_rect.width,
plane_state->dst_rect.height,
plane_state->clip_rect.x,
plane_state->clip_rect.y,
plane_state->clip_rect.width,
plane_state->clip_rect.height);
SURFACE_TRACE(
"surface->plane_size.grph.surface_size.x = %d;\n"
"surface->plane_size.grph.surface_size.y = %d;\n"
"surface->plane_size.grph.surface_size.width = %d;\n"
"surface->plane_size.grph.surface_size.height = %d;\n"
"surface->plane_size.grph.surface_pitch = %d;\n",
surface->plane_size.grph.surface_size.x,
surface->plane_size.grph.surface_size.y,
surface->plane_size.grph.surface_size.width,
surface->plane_size.grph.surface_size.height,
surface->plane_size.grph.surface_pitch);
"plane_state->plane_size.grph.surface_size.x = %d;\n"
"plane_state->plane_size.grph.surface_size.y = %d;\n"
"plane_state->plane_size.grph.surface_size.width = %d;\n"
"plane_state->plane_size.grph.surface_size.height = %d;\n"
"plane_state->plane_size.grph.surface_pitch = %d;\n",
plane_state->plane_size.grph.surface_size.x,
plane_state->plane_size.grph.surface_size.y,
plane_state->plane_size.grph.surface_size.width,
plane_state->plane_size.grph.surface_size.height,
plane_state->plane_size.grph.surface_pitch);
SURFACE_TRACE(
"surface->tiling_info.gfx8.num_banks = %d;\n"
"surface->tiling_info.gfx8.bank_width = %d;\n"
"surface->tiling_info.gfx8.bank_width_c = %d;\n"
"surface->tiling_info.gfx8.bank_height = %d;\n"
"surface->tiling_info.gfx8.bank_height_c = %d;\n"
"surface->tiling_info.gfx8.tile_aspect = %d;\n"
"surface->tiling_info.gfx8.tile_aspect_c = %d;\n"
"surface->tiling_info.gfx8.tile_split = %d;\n"
"surface->tiling_info.gfx8.tile_split_c = %d;\n"
"surface->tiling_info.gfx8.tile_mode = %d;\n"
"surface->tiling_info.gfx8.tile_mode_c = %d;\n",
surface->tiling_info.gfx8.num_banks,
surface->tiling_info.gfx8.bank_width,
surface->tiling_info.gfx8.bank_width_c,
surface->tiling_info.gfx8.bank_height,
surface->tiling_info.gfx8.bank_height_c,
surface->tiling_info.gfx8.tile_aspect,
surface->tiling_info.gfx8.tile_aspect_c,
surface->tiling_info.gfx8.tile_split,
surface->tiling_info.gfx8.tile_split_c,
surface->tiling_info.gfx8.tile_mode,
surface->tiling_info.gfx8.tile_mode_c);
"plane_state->tiling_info.gfx8.num_banks = %d;\n"
"plane_state->tiling_info.gfx8.bank_width = %d;\n"
"plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
"plane_state->tiling_info.gfx8.bank_height = %d;\n"
"plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
"plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
"plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
"plane_state->tiling_info.gfx8.tile_split = %d;\n"
"plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
"plane_state->tiling_info.gfx8.tile_mode = %d;\n"
"plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
plane_state->tiling_info.gfx8.num_banks,
plane_state->tiling_info.gfx8.bank_width,
plane_state->tiling_info.gfx8.bank_width_c,
plane_state->tiling_info.gfx8.bank_height,
plane_state->tiling_info.gfx8.bank_height_c,
plane_state->tiling_info.gfx8.tile_aspect,
plane_state->tiling_info.gfx8.tile_aspect_c,
plane_state->tiling_info.gfx8.tile_split,
plane_state->tiling_info.gfx8.tile_split_c,
plane_state->tiling_info.gfx8.tile_mode,
plane_state->tiling_info.gfx8.tile_mode_c);
SURFACE_TRACE(
"surface->tiling_info.gfx8.pipe_config = %d;\n"
"surface->tiling_info.gfx8.array_mode = %d;\n"
"surface->color_space = %d;\n"
"surface->dcc.enable = %d;\n"
"surface->format = %d;\n"
"surface->rotation = %d;\n"
"surface->stereo_format = %d;\n",
surface->tiling_info.gfx8.pipe_config,
surface->tiling_info.gfx8.array_mode,
surface->color_space,
surface->dcc.enable,
surface->format,
surface->rotation,
surface->stereo_format);
SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
surface->tiling_info.gfx9.swizzle);
"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
"plane_state->tiling_info.gfx8.array_mode = %d;\n"
"plane_state->color_space = %d;\n"
"plane_state->dcc.enable = %d;\n"
"plane_state->format = %d;\n"
"plane_state->rotation = %d;\n"
"plane_state->stereo_format = %d;\n",
plane_state->tiling_info.gfx8.pipe_config,
plane_state->tiling_info.gfx8.array_mode,
plane_state->color_space,
plane_state->dcc.enable,
plane_state->format,
plane_state->rotation,
plane_state->stereo_format);
SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
plane_state->tiling_info.gfx9.swizzle);
SURFACE_TRACE("\n");
}
......
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View file @ 3be5262e
......@@ -185,7 +185,7 @@ bool dc_stream_set_cursor_attributes(
if (pipe_ctx->stream != stream || !pipe_ctx->ipp)
continue;
if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface)
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
continue;
pipe_ctx->ipp->funcs->ipp_cursor_set_attributes(
......@@ -229,14 +229,14 @@ bool dc_stream_set_cursor_position(
};
if (pipe_ctx->stream != stream ||
!pipe_ctx->ipp || !pipe_ctx->surface)
!pipe_ctx->ipp || !pipe_ctx->plane_state)
continue;
if (pipe_ctx->surface->address.type
if (pipe_ctx->plane_state->address.type
== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
pos_cpy.enable = false;
if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface)
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
pos_cpy.enable = false;
ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
......
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
View file @ 3be5262e
......@@ -34,75 +34,75 @@
/*******************************************************************************
* Private functions
******************************************************************************/
static bool construct(struct dc_context *ctx, struct dc_plane_state *surface)
static bool construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
{
surface->ctx = ctx;
memset(&surface->hdr_static_ctx,
plane_state->ctx = ctx;
memset(&plane_state->hdr_static_ctx,
0, sizeof(struct dc_hdr_static_metadata));
return true;
}
static void destruct(struct dc_plane_state *surface)
static void destruct(struct dc_plane_state *plane_state)
{
if (surface->gamma_correction != NULL) {
dc_gamma_release(&surface->gamma_correction);
if (plane_state->gamma_correction != NULL) {
dc_gamma_release(&plane_state->gamma_correction);
}
if (surface->in_transfer_func != NULL) {
if (plane_state->in_transfer_func != NULL) {
dc_transfer_func_release(
surface->in_transfer_func);
surface->in_transfer_func = NULL;
plane_state->in_transfer_func);
plane_state->in_transfer_func = NULL;
}
}
/*******************************************************************************
* Public functions
******************************************************************************/
void enable_surface_flip_reporting(struct dc_plane_state *surface,
void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
uint32_t controller_id)
{
surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
/*register_flip_interrupt(surface);*/
}
struct dc_plane_state *dc_create_surface(const struct dc *dc)
struct dc_plane_state *dc_create_plane_state(const struct dc *dc)
{
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc_plane_state *surface = dm_alloc(sizeof(*surface));
struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state));
if (NULL == surface)
if (NULL == plane_state)
goto alloc_fail;
if (false == construct(core_dc->ctx, surface))
if (false == construct(core_dc->ctx, plane_state))
goto construct_fail;
++surface->ref_count;
++plane_state->ref_count;
return surface;
return plane_state;
construct_fail:
dm_free(surface);
dm_free(plane_state);
alloc_fail:
return NULL;
}
const struct dc_surface_status *dc_surface_get_status(
const struct dc_plane_state *dc_surface)
const struct dc_plane_status *dc_plane_get_status(
const struct dc_plane_state *plane_state)
{
const struct dc_surface_status *surface_status;
const struct dc_plane_status *plane_status;
struct core_dc *core_dc;
int i;
if (!dc_surface ||
!dc_surface->ctx ||
!dc_surface->ctx->dc) {
if (!plane_state ||
!plane_state->ctx ||
!plane_state->ctx->dc) {
ASSERT(0);
return NULL; /* remove this if above assert never hit */
}
surface_status = &dc_surface->status;
core_dc = DC_TO_CORE(dc_surface->ctx->dc);
plane_status = &plane_state->status;
core_dc = DC_TO_CORE(plane_state->ctx->dc);
if (core_dc->current_context == NULL)
return NULL;
......@@ -111,29 +111,29 @@ const struct dc_surface_status *dc_surface_get_status(
struct pipe_ctx *pipe_ctx =
&core_dc->current_context->res_ctx.pipe_ctx[i];
if (pipe_ctx->surface != dc_surface)
if (pipe_ctx->plane_state != plane_state)
continue;
core_dc->hwss.update_pending_status(pipe_ctx);
}
return surface_status;
return plane_status;
}
void dc_surface_retain(struct dc_plane_state *surface)
void dc_plane_state_retain(struct dc_plane_state *plane_state)
{
ASSERT(surface->ref_count > 0);
++surface->ref_count;
ASSERT(plane_state->ref_count > 0);
++plane_state->ref_count;
}
void dc_surface_release(struct dc_plane_state *surface)
void dc_plane_state_release(struct dc_plane_state *plane_state)
{
ASSERT(surface->ref_count > 0);
--surface->ref_count;
ASSERT(plane_state->ref_count > 0);
--plane_state->ref_count;
if (surface->ref_count == 0) {
destruct(surface);
dm_free(surface);
if (plane_state->ref_count == 0) {
destruct(plane_state);
dm_free(plane_state);
}
}
......
drivers/gpu/drm/amd/display/dc/dc.h
View file @ 3be5262e
......@@ -47,7 +47,7 @@ struct dc_caps {
uint32_t max_links;
uint32_t max_audios;
uint32_t max_slave_planes;
uint32_t max_surfaces;
uint32_t max_planes;
uint32_t max_downscale_ratio;
uint32_t i2c_speed_in_khz;
......@@ -303,7 +303,7 @@ struct dc_transfer_func {
* the last requested address and the currently active address so the called
* can determine if there are any outstanding flips
*/
struct dc_surface_status {
struct dc_plane_status {
struct dc_plane_address requested_address;
struct dc_plane_address current_address;
bool is_flip_pending;
......@@ -338,7 +338,7 @@ struct dc_plane_state {
bool horizontal_mirror;
/* private to DC core */
struct dc_surface_status status;
struct dc_plane_status status;
struct dc_context *ctx;
/* private to dc_surface.c */
......@@ -385,12 +385,12 @@ struct dc_surface_update {
/*
* Create a new surface with default parameters;
*/
struct dc_plane_state *dc_create_surface(const struct dc *dc);
const struct dc_surface_status *dc_surface_get_status(
const struct dc_plane_state *dc_surface);
struct dc_plane_state *dc_create_plane_state(const struct dc *dc);
const struct dc_plane_status *dc_plane_get_status(
const struct dc_plane_state *plane_state);
void dc_surface_retain(struct dc_plane_state *dc_surface);
void dc_surface_release(struct dc_plane_state *dc_surface);
void dc_plane_state_retain(struct dc_plane_state *plane_state);
void dc_plane_state_release(struct dc_plane_state *plane_state);
void dc_gamma_retain(struct dc_gamma *dc_gamma);
void dc_gamma_release(struct dc_gamma **dc_gamma);
......@@ -422,10 +422,10 @@ struct dc_flip_addrs {
* This does not trigger a flip. No surface address is programmed.
*/
bool dc_commit_surfaces_to_stream(
bool dc_commit_planes_to_stream(
struct dc *dc,
struct dc_plane_state **dc_surfaces,
uint8_t surface_count,
struct dc_plane_state **plane_states,
uint8_t new_plane_count,
struct dc_stream_state *stream);
bool dc_post_update_surfaces_to_stream(
......@@ -469,8 +469,8 @@ enum surface_update_type {
struct dc_stream_status {
int primary_otg_inst;
int surface_count;
struct dc_plane_state *surfaces[MAX_SURFACE_NUM];
int plane_count;
struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
/*
* link this stream passes through
......@@ -546,7 +546,7 @@ bool dc_is_stream_unchanged(
*
*/
void dc_update_surfaces_and_stream(struct dc *dc,
void dc_update_planes_and_stream(struct dc *dc,
struct dc_surface_update *surface_updates, int surface_count,
struct dc_stream_state *dc_stream,
struct dc_stream_update *stream_update);
......@@ -582,8 +582,8 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
*/
struct dc_validation_set {
struct dc_stream_state *stream;
struct dc_plane_state *surfaces[MAX_SURFACES];
uint8_t surface_count;
struct dc_plane_state *plane_states[MAX_SURFACES];
uint8_t plane_count;
};
bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream);
......
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
View file @ 3be5262e
......@@ -197,9 +197,9 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
}
/* Only use LUT for 8 bit formats */
bool dce_use_lut(const struct dc_plane_state *surface)
bool dce_use_lut(const struct dc_plane_state *plane_state)
{
switch (surface->format) {
switch (plane_state->format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
return true;
......
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
View file @ 3be5262e
......@@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst);
bool dce_use_lut(const struct dc_plane_state *surface);
bool dce_use_lut(const struct dc_plane_state *plane_state);
#endif /*__DCE_HWSEQ_H__*/
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View file @ 3be5262e
......@@ -705,13 +705,13 @@ static bool dce100_validate_surface_sets(
int i;
for (i = 0; i < set_count; i++) {
if (set[i].surface_count == 0)
if (set[i].plane_count == 0)
continue;
if (set[i].surface_count > 1)
if (set[i].plane_count > 1)
return false;
if (set[i].surfaces[0]->format
if (set[i].plane_states[0]->format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
}
......@@ -958,7 +958,7 @@ static bool construct(
}
}
dc->public.caps.max_surfaces = pool->base.pipe_count;
dc->public.caps.max_planes = pool->base.pipe_count;
if (!resource_construct(num_virtual_links, dc, &pool->base,
&res_create_funcs))
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file @ 3be5262e
......@@ -215,11 +215,11 @@ static bool dce110_enable_display_power_gating(
}
static void build_prescale_params(struct ipp_prescale_params *prescale_params,
const struct dc_plane_state *surface)
const struct dc_plane_state *plane_state)
{
prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
switch (surface->format) {
switch (plane_state->format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
prescale_params->scale = 0x2020;
......@@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
static bool dce110_set_input_transfer_func(
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *surface)
const struct dc_plane_state *plane_state)
{
struct input_pixel_processor *ipp = pipe_ctx->ipp;
const struct dc_transfer_func *tf = NULL;
......@@ -250,14 +250,14 @@ static bool dce110_set_input_transfer_func(
if (ipp == NULL)
return false;
if (surface->in_transfer_func)
tf = surface->in_transfer_func;
if (plane_state->in_transfer_func)
tf = plane_state->in_transfer_func;
build_prescale_params(&prescale_params, surface);
build_prescale_params(&prescale_params, plane_state);
ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
if (surface->gamma_correction && dce_use_lut(surface))
ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction);
if (plane_state->gamma_correction && dce_use_lut(plane_state))
ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
if (tf == NULL) {
/* Default case if no input transfer function specified */
......@@ -1119,7 +1119,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if ((!pipe_ctx_old ||
memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data,
sizeof(struct scaler_data)) != 0) &&
pipe_ctx->surface) {
pipe_ctx->plane_state) {
program_scaler(dc, pipe_ctx);
}
......@@ -1916,11 +1916,11 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
struct default_adjustment default_adjust = { 0 };
default_adjust.force_hw_default = false;
if (pipe_ctx->surface == NULL)
if (pipe_ctx->plane_state == NULL)
default_adjust.in_color_space = COLOR_SPACE_SRGB;
else
default_adjust.in_color_space =
pipe_ctx->surface->color_space;
pipe_ctx->plane_state->color_space;
if (pipe_ctx->stream == NULL)
default_adjust.out_color_space = COLOR_SPACE_SRGB;
else
......@@ -1971,16 +1971,16 @@ static void program_surface_visibility(const struct core_dc *dc,
/* For now we are supporting only two pipes */
ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
if (pipe_ctx->bottom_pipe->surface->visible) {
if (pipe_ctx->surface->visible)
if (pipe_ctx->bottom_pipe->plane_state->visible) {
if (pipe_ctx->plane_state->visible)
blender_mode = BLND_MODE_BLENDING;
else
blender_mode = BLND_MODE_OTHER_PIPE;
} else if (!pipe_ctx->surface->visible)
} else if (!pipe_ctx->plane_state->visible)
blank_target = true;
} else if (!pipe_ctx->surface->visible)
} else if (!pipe_ctx->plane_state->visible)
blank_target = true;
dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
......@@ -2038,7 +2038,7 @@ static void set_plane_config(
struct resource_context *res_ctx)
{
struct mem_input *mi = pipe_ctx->mi;
struct dc_plane_state *surface = pipe_ctx->surface;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
unsigned int i;
......@@ -2103,57 +2103,57 @@ static void set_plane_config(
mi->funcs->mem_input_program_surface_config(
mi,
surface->format,
&surface->tiling_info,
&surface->plane_size,
surface->rotation,
plane_state->format,
&plane_state->tiling_info,
&plane_state->plane_size,
plane_state->rotation,
NULL,
false);
if (mi->funcs->set_blank)
mi->funcs->set_blank(mi, pipe_ctx->surface->visible);
mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
pipe_ctx->mi,
surface->format,
&surface->tiling_info,
surface->rotation);
plane_state->format,
&plane_state->tiling_info,
plane_state->rotation);
}
static void update_plane_addr(const struct core_dc *dc,
struct pipe_ctx *pipe_ctx)
{
struct dc_plane_state *surface = pipe_ctx->surface;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
if (surface == NULL)
if (plane_state == NULL)
return;
pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
pipe_ctx->mi,
&surface->address,
surface->flip_immediate);
&plane_state->address,
plane_state->flip_immediate);
surface->status.requested_address = surface->address;
plane_state->status.requested_address = plane_state->address;
}
void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
{
struct dc_plane_state *surface = pipe_ctx->surface;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
if (surface == NULL)
if (plane_state == NULL)
return;
surface->status.is_flip_pending =
plane_state->status.is_flip_pending =
pipe_ctx->mi->funcs->mem_input_is_flip_pending(
pipe_ctx->mi);
if (surface->status.is_flip_pending && !surface->visible)
if (plane_state->status.is_flip_pending && !plane_state->visible)
pipe_ctx->mi->current_address = pipe_ctx->mi->request_address;
surface->status.current_address = pipe_ctx->mi->current_address;
plane_state->status.current_address = pipe_ctx->mi->current_address;
if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
pipe_ctx->tg->funcs->is_stereo_left_eye) {
surface->status.is_right_eye =\
plane_state->status.is_right_eye =\
!pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
}
}
......@@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe(
{
struct mem_input *mi = pipe_ctx->mi;
struct pipe_ctx *old_pipe = NULL;
struct dc_plane_state *surface = pipe_ctx->surface;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
unsigned int i;
......@@ -2558,21 +2558,21 @@ static void dce110_program_front_end_for_pipe(
mi->funcs->mem_input_program_surface_config(
mi,
surface->format,
&surface->tiling_info,
&surface->plane_size,
surface->rotation,
plane_state->format,
&plane_state->tiling_info,
&plane_state->plane_size,
plane_state->rotation,
NULL,
false);
if (mi->funcs->set_blank)
mi->funcs->set_blank(mi, pipe_ctx->surface->visible);
mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
pipe_ctx->mi,
surface->format,
&surface->tiling_info,
surface->rotation);
plane_state->format,
&plane_state->tiling_info,
plane_state->rotation);
dm_logger_write(dc->ctx->logger, LOG_SURFACE,
"Pipe:%d 0x%x: addr hi:0x%x, "
......@@ -2581,21 +2581,21 @@ static void dce110_program_front_end_for_pipe(
" %d; dst: %d, %d, %d, %d;"
"clip: %d, %d, %d, %d\n",
pipe_ctx->pipe_idx,
pipe_ctx->surface,
pipe_ctx->surface->address.grph.addr.high_part,
pipe_ctx->surface->address.grph.addr.low_part,
pipe_ctx->surface->src_rect.x,
pipe_ctx->surface->src_rect.y,
pipe_ctx->surface->src_rect.width,
pipe_ctx->surface->src_rect.height,
pipe_ctx->surface->dst_rect.x,
pipe_ctx->surface->dst_rect.y,
pipe_ctx->surface->dst_rect.width,
pipe_ctx->surface->dst_rect.height,
pipe_ctx->surface->clip_rect.x,
pipe_ctx->surface->clip_rect.y,
pipe_ctx->surface->clip_rect.width,
pipe_ctx->surface->clip_rect.height);
pipe_ctx->plane_state,
pipe_ctx->plane_state->address.grph.addr.high_part,
pipe_ctx->plane_state->address.grph.addr.low_part,
pipe_ctx->plane_state->src_rect.x,
pipe_ctx->plane_state->src_rect.y,
pipe_ctx->plane_state->src_rect.width,
pipe_ctx->plane_state->src_rect.height,
pipe_ctx->plane_state->dst_rect.x,
pipe_ctx->plane_state->dst_rect.y,
pipe_ctx->plane_state->dst_rect.width,
pipe_ctx->plane_state->dst_rect.height,
pipe_ctx->plane_state->clip_rect.x,
pipe_ctx->plane_state->clip_rect.y,
pipe_ctx->plane_state->clip_rect.width,
pipe_ctx->plane_state->clip_rect.height);
dm_logger_write(dc->ctx->logger, LOG_SURFACE,
"Pipe %d: width, height, x, y\n"
......@@ -2614,19 +2614,18 @@ static void dce110_program_front_end_for_pipe(
static void dce110_apply_ctx_for_surface(
struct core_dc *dc,
const struct dc_plane_state *surface,
const struct dc_plane_state *plane_state,
struct validate_context *context)
{
int i;
/* TODO remove when removing the surface reset workaroud*/
if (!surface)
if (!plane_state)
return;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
if (pipe_ctx->surface != surface)
if (pipe_ctx->plane_state != plane_state)
continue;
dce110_program_front_end_for_pipe(dc, pipe_ctx);
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View file @ 3be5262e
......@@ -764,9 +764,9 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne
{
if (pipe_ctx->pipe_idx != underlay_idx)
return true;
if (!pipe_ctx->surface)
if (!pipe_ctx->plane_state)
return false;
if (pipe_ctx->surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
return true;
}
......@@ -901,22 +901,22 @@ static bool dce110_validate_surface_sets(
int i;
for (i = 0; i < set_count; i++) {
if (set[i].surface_count == 0)
if (set[i].plane_count == 0)
continue;
if (set[i].surface_count > 2)
if (set[i].plane_count > 2)
return false;
if (set[i].surfaces[0]->format
if (set[i].plane_states[0]->format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
if (set[i].surface_count == 2) {
if (set[i].surfaces[1]->format
if (set[i].plane_count == 2) {
if (set[i].plane_states[1]->format
< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
if (set[i].surfaces[1]->src_rect.width > 1920
|| set[i].surfaces[1]->src_rect.height > 1080)
if (set[i].plane_states[1]->src_rect.width > 1920
|| set[i].plane_states[1]->src_rect.height > 1080)
return false;
if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB)
......@@ -1351,7 +1351,7 @@ static bool construct(
if (!dce110_hw_sequencer_construct(dc))
goto res_create_fail;
dc->public.caps.max_surfaces = pool->base.pipe_count;
dc->public.caps.max_planes = pool->base.pipe_count;
bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
......
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View file @ 3be5262e
......@@ -889,13 +889,13 @@ static bool dce112_validate_surface_sets(
int i;
for (i = 0; i < set_count; i++) {
if (set[i].surface_count == 0)
if (set[i].plane_count == 0)
continue;
if (set[i].surface_count > 1)
if (set[i].plane_count > 1)
return false;
if (set[i].surfaces[0]->format
if (set[i].plane_states[0]->format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
}
......@@ -1319,7 +1319,7 @@ static bool construct(
&res_create_funcs))
goto res_create_fail;
dc->public.caps.max_surfaces = pool->base.pipe_count;
dc->public.caps.max_planes = pool->base.pipe_count;
/* Create hardware sequencer */
if (!dce112_hw_sequencer_construct(dc))
......
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View file @ 3be5262e
......@@ -982,7 +982,7 @@ static bool construct(
if (!dce120_hw_sequencer_create(dc))
goto controller_create_fail;
dc->public.caps.max_surfaces = pool->base.pipe_count;
dc->public.caps.max_planes = pool->base.pipe_count;
bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
......
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View file @ 3be5262e
......@@ -722,13 +722,13 @@ static bool dce80_validate_surface_sets(
int i;
for (i = 0; i < set_count; i++) {
if (set[i].surface_count == 0)
if (set[i].plane_count == 0)
continue;
if (set[i].surface_count > 1)
if (set[i].plane_count > 1)
return false;
if (set[i].surfaces[0]->format
if (set[i].plane_states[0]->format
>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return false;
}
......@@ -959,7 +959,7 @@ static bool construct(
}
}
dc->public.caps.max_surfaces = pool->base.pipe_count;
dc->public.caps.max_planes = pool->base.pipe_count;
if (!resource_construct(num_virtual_links, dc, &pool->base,
&res_create_funcs))
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View file @ 3be5262e
......@@ -1406,7 +1406,7 @@ static bool construct(
goto res_create_fail;
dcn10_hw_sequencer_construct(dc);
dc->public.caps.max_surfaces = pool->base.pipe_count;
dc->public.caps.max_planes = pool->base.pipe_count;
dc->public.cap_funcs = cap_funcs;
......
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View file @ 3be5262e
......@@ -36,7 +36,7 @@
#define MAX_CLOCK_SOURCES 7
void enable_surface_flip_reporting(struct dc_plane_state *dc_surface,
void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
uint32_t controller_id);
#include "grph_object_id.h"
......@@ -153,7 +153,7 @@ struct resource_pool {
};
struct pipe_ctx {
struct dc_plane_state *surface;
struct dc_plane_state *plane_state;
struct dc_stream_state *stream;
struct mem_input *mi;
......
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View file @ 3be5262e
......@@ -59,7 +59,7 @@ struct hw_sequencer_funcs {
void (*apply_ctx_for_surface)(
struct core_dc *dc,
const struct dc_plane_state *surface,
const struct dc_plane_state *plane_state,
struct validate_context *context);
void (*set_plane_config)(
......@@ -88,7 +88,7 @@ struct hw_sequencer_funcs {
bool (*set_input_transfer_func)(
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *surface);
const struct dc_plane_state *plane_state);
bool (*set_output_transfer_func)(
struct pipe_ctx *pipe_ctx,
......
drivers/gpu/drm/amd/display/dc/inc/resource.h
View file @ 3be5262e
......@@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
struct dc_stream_state *stream);
bool resource_attach_surfaces_to_context(
struct dc_plane_state *const *surfaces,
struct dc_plane_state *const *plane_state,
int surface_count,
struct dc_stream_state *dc_stream,
struct validate_context *context,
......
drivers/gpu/drm/amd/display/include/logger_interface.h
View file @ 3be5262e
......@@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger,
void pre_surface_trace(
const struct dc *dc,
const struct dc_plane_state *const *surfaces,
const struct dc_plane_state *const *plane_states,
int surface_count);
void update_surface_trace(
......
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