Commit 3d7db0f1 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mark Brown

spi: dw: Refactor mid_spi_dma_setup() to separate DMA and IRQ config

It's better to understand what bits are set for DMA and for IRQ handling
in mid_spi_dma_setup() if they are grouped accordingly. Thus,
refactor mid_spi_dma_setup() to separate DMA and IRQ configuration.
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200529183150.44149-2-andriy.shevchenko@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent b3f82dc2
...@@ -375,17 +375,17 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) ...@@ -375,17 +375,17 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst); dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
if (xfer->tx_buf) { if (xfer->tx_buf)
dma_ctrl |= SPI_DMA_TDMAE; dma_ctrl |= SPI_DMA_TDMAE;
imr |= SPI_INT_TXOI; if (xfer->rx_buf)
}
if (xfer->rx_buf) {
dma_ctrl |= SPI_DMA_RDMAE; dma_ctrl |= SPI_DMA_RDMAE;
imr |= SPI_INT_RXUI | SPI_INT_RXOI;
}
dw_writel(dws, DW_SPI_DMACR, dma_ctrl); dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
/* Set the interrupt mask */ /* Set the interrupt mask */
if (xfer->tx_buf)
imr |= SPI_INT_TXOI;
if (xfer->rx_buf)
imr |= SPI_INT_RXUI | SPI_INT_RXOI;
spi_umask_intr(dws, imr); spi_umask_intr(dws, imr);
reinit_completion(&dws->dma_completion); reinit_completion(&dws->dma_completion);
......
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