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Commit 3f52326a authored by dmitry pervushin's avatar dmitry pervushin Committed by Russell King
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[ARM] 5531/1: Freescale STMP: get rid of HW_zzz macros [2/3] 

Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls
Signed-off-by: default avatardmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e0421bbe
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arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
View file @ 3f52326a
/*
* STMP APBH Register Definitions
* stmp37xx: APBH register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
......@@ -18,85 +18,80 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H
#define _INCLUDE_ASM_ARCH_REGS_APBH_H
#ifndef _MACH_REGS_APBH
#define _MACH_REGS_APBH
#include <mach/stmp3xxx_regs.h>
#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
#ifndef REGS_APBH_BASE
#define REGS_APBH_BASE (REGS_BASE + 0x00004000)
#endif
#define HW_APBH_CTRL0 0x0
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
#define BP_APBH_CTRL0_RESET_CHANNEL 16
#define BM_APBH_CTRL0_CLKGATE 0x40000000
#define BM_APBH_CTRL0_SFTRST 0x80000000
#define HW_APBH_CTRL1 0x10
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
#define HW_APBH_DEVSEL 0x20
#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)
#define BP_APBH_CTRL0_SFTRST 31
#define BM_APBH_CTRL0_SFTRST 0x80000000
#define BP_APBH_CTRL0_CLKGATE 30
#define BM_APBH_CTRL0_CLKGATE 0x40000000
#define BP_APBH_CTRL0_RESET_CHANNEL 16
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
(((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 9
#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00000200
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 8
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00000100
#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7
#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080
#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1
#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
#define BP_APBH_CTRL1_CH1_ERR_IRQ 17
#define BM_APBH_CTRL1_CH1_ERR_IRQ 0x00020000
HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0
#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBH_CHn_CMD_XFER_COUNT 16
#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
(((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBH_CHn_CMD_CMDWORDS 12
#define BF_APBH_CHn_CMD_CMDWORDS(v) \
(((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
#define BP_APBH_CHn_CMD_SEMAPHORE 6
#define BF_APBH_CHn_CMD_SEMAPHORE(v) \
(((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
#define BP_APBH_CHn_CMD_NANDLOCK 4
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
#define BF_APBH_CHn_CMD_NANDLOCK(v) \
(((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
#define HW_APBH_CHn_NXTCMDAR 0x50
#define BM_APBH_CHn_CMD_MODE 0x00000003
#define BP_APBH_CHn_CMD_MODE 0x00000001
#define BV_APBH_CHn_CMD_MODE_NOOP 0
#define BV_APBH_CHn_CMD_MODE_WRITE 1
#define BV_APBH_CHn_CMD_MODE_READ 2
#define BV_APBH_CHn_CMD_MODE_SENSE 3
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
#define BM_APBH_CHn_CMD_DMA_READ 0x00000003
#define BP_APBH_CHn_CMD_DMA_READ 0
#define BF_APBH_CHn_CMD_DMA_READ(v) \
(((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
#define BF_APBH_CHn_CMD_COMMAND(v) \
(((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)
HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
(((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \
BM_APBH_CHn_SEMA_INCREMENT_SEMA)
#define BP_APBH_CHn_SEMA_PHORE 16
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)
HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)
HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBH_CHn_CMD_CMDWORDS 12
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBH_CHn_CMD_XFER_COUNT 16
#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */
#define HW_APBH_CHn_SEMA 0x80
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
#define BP_APBH_CHn_SEMA_PHORE 16
#endif
arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
View file @ 3f52326a
/*
* STMP APBX Register Definitions
* stmp37xx: APBX register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
......@@ -18,92 +18,96 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H
#define _INCLUDE_ASM_ARCH_REGS_APBX_H
#ifndef _MACH_REGS_APBX
#define _MACH_REGS_APBX
#include <mach/stmp3xxx_regs.h>
#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
#ifndef REGS_APBX_BASE
#define REGS_APBX_BASE (REGS_BASE + 0x00024000)
#endif
#define HW_APBX_CTRL0 0x0
#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
#define BP_APBX_CTRL0_RESET_CHANNEL 16
#define BM_APBX_CTRL0_CLKGATE 0x40000000
#define BM_APBX_CTRL0_SFTRST 0x80000000
#define HW_APBX_CTRL1 0x10
#define HW_APBX_DEVSEL 0x20
#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00)
#define BP_APBX_CTRL0_SFTRST 31
#define BM_APBX_CTRL0_SFTRST 0x80000000
#define BP_APBX_CTRL0_CLKGATE 30
#define BM_APBX_CTRL0_CLKGATE 0x40000000
#define BP_APBX_CTRL0_RESET_CHANNEL 16
#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
#define BF_APBX_CTRL0_RESET_CHANNEL(v) \
(((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL)
HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10)
HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20)
#define BP_APBX_DEVSEL_CH7 28
#define BM_APBX_DEVSEL_CH7 0xF0000000
#define BF_APBX_DEVSEL_CH7(v) \
(((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7)
#define BV_APBX_DEVSEL_CH7__USE_UART 0x0
#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1
#define BP_APBX_DEVSEL_CH6 24
#define BM_APBX_DEVSEL_CH6 0x0F000000
#define BF_APBX_DEVSEL_CH6(v) \
(((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6)
#define BV_APBX_DEVSEL_CH6__USE_UART 0x0
#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1
#define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23
#define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000
#define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22
#define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000
#define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15
#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000
#define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14
#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000
#define HW_APBX_CHn_NXTCMDAR 0x50
#define BM_APBX_CHn_CMD_MODE 0x00000003
#define BP_APBX_CHn_CMD_MODE 0x00000001
#define BV_APBX_CHn_CMD_MODE_NOOP 0
#define BV_APBX_CHn_CMD_MODE_WRITE 1
#define BV_APBX_CHn_CMD_MODE_READ 2
#define BV_APBX_CHn_CMD_MODE_SENSE 3
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
#define BP_APBX_CHn_CMD_COMMAND 0
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBX_CHn_CMD_CMDWORDS 12
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBX_CHn_CMD_XFER_COUNT 16
HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70)
HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70)
#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0
#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70)
#define BP_APBX_CHn_CMD_XFER_COUNT 16
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BF_APBX_CHn_CMD_XFER_COUNT(v) \
(((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT)
#define BP_APBX_CHn_CMD_CMDWORDS 12
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
#define BF_APBX_CHn_CMD_CMDWORDS(v) \
(((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS)
#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BP_APBX_CHn_CMD_SEMAPHORE 6
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
#define BP_APBX_CHn_CMD_IRQONCMPLT 3
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
#define BP_APBX_CHn_CMD_CHAIN 2
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
#define BM_APBX_CHn_CMD_DMA_READ 0x00000003
#define BP_APBX_CHn_CMD_DMA_READ 0
#define BF_APBX_CHn_CMD_DMA_READ(v) \
(((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ)
#define BP_APBX_CHn_CMD_COMMAND 0
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
#define BF_APBX_CHn_CMD_COMMAND(v) \
(((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND)
#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70)
HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70)
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \
(((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \
BM_APBX_CHn_SEMA_INCREMENT_SEMA)
#define BP_APBX_CHn_SEMA_PHORE 16
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70)
HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70)
HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0)
#define HW_APBX_CHn_BAR 0x70
#endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */
#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
#define HW_APBX_CHn_SEMA 0x80
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
#define BP_APBX_CHn_SEMA_PHORE 16
#endif
arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
View file @ 3f52326a
#ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H
#define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H
/*
* stmp37xx: CLKCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_CLKCTRL
#define _MACH_REGS_CLKCTRL
#include <mach/stmp3xxx_regs.h>
#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
#define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000)
#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00)
HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00)
#define HW_CLKCTRL_PLLCTRL0 0x0
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x10)
HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10)
#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x20)
HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20)
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
#define BF_CLKCTRL_CPU_DIV_CPU(v) \
(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x30)
HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30)
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0 /* for compatitibility */
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
#define BF_CLKCTRL_HBUS_DIV(v) \
(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x40)
HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40)
#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x50)
HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50)
#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x60)
HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60)
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
#define BM_CLKCTRL_PIX_BUSY 0x20000000
#define BM_CLKCTRL_PIX_DIV 0x00007FFF
#define BP_CLKCTRL_PIX_DIV 0
#define BF_CLKCTRL_PIX_DIV(v) \
(((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV)
#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x70)
HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70)
#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x80)
HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80)
#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x90)
HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90)
#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0xA0)
HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0)
#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0xB0)
HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0)
#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0xC0)
HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0)
#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0xD0)
HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0)
#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
#define BP_CLKCTRL_FRAC_IOFRAC 24
#define BF_CLKCTRL_FRAC_IOFRAC(v) \
(((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC)
#define HW_CLKCTRL_CPU 0x20
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
#define BP_CLKCTRL_CPU_DIV_CPU 0
#define HW_CLKCTRL_HBUS 0x30
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
#define BP_CLKCTRL_HBUS_DIV 0
#define HW_CLKCTRL_XBUS 0x40
#define HW_CLKCTRL_XTAL 0x50
#define HW_CLKCTRL_PIX 0x60
#define BM_CLKCTRL_PIX_DIV 0x00007FFF
#define BP_CLKCTRL_PIX_DIV 0
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
#define HW_CLKCTRL_SSP 0x70
#define HW_CLKCTRL_GPMI 0x80
#define HW_CLKCTRL_SPDIF 0x90
#define HW_CLKCTRL_EMI 0xA0
#define HW_CLKCTRL_IR 0xB0
#define HW_CLKCTRL_SAIF 0xC0
#define HW_CLKCTRL_FRAC 0xD0
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
#define BP_CLKCTRL_FRAC_EMIFRAC 8
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
#define BP_CLKCTRL_FRAC_PIXFRAC 16
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
#define BP_CLKCTRL_FRAC_PIXFRAC 16
#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
(((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC)
#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
#define BP_CLKCTRL_FRAC_EMIFRAC 8
#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
(((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC)
#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
#define BP_CLKCTRL_FRAC_CPUFRAC 0
#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
(((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC)
#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0xE0)
HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0)
#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0)
#define BM_CLKCTRL_RESET_CHIP 0x00000002
#define BM_CLKCTRL_RESET_DIG 0x00000001
#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */
#define HW_CLKCTRL_CLKSEQ 0xE0
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
#define HW_CLKCTRL_RESET 0xF0
#define BM_CLKCTRL_RESET_DIG 0x00000001
#define BP_CLKCTRL_RESET_DIG 0
#endif
arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
View file @ 3f52326a
/*
* Freescale STMP378X: clock registers definitions
* stmp37xx: ICOLL register definitions
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_ICOLL
#define _MACH_REGS_ICOLL
#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
#ifndef _INCLUDE_ASM_ARCH_REGS_ICOLL_H
#define _INCLUDE_ASM_ARCH_REGS_ICOLL_H
#define HW_ICOLL_VECTOR 0x0
#define HW_ICOLL_LEVELACK 0x10
#include <mach/stmp3xxx_regs.h>
#define HW_ICOLL_CTRL 0x20
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
#define BM_ICOLL_CTRL_SFTRST 0x80000000
#define REGS_ICOLL_BASE (REGS_BASE + 0x00000000)
#define HW_ICOLL_STAT 0x30
HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00)
HW_REGISTER_WO(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x10)
HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x20)
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
#define BM_ICOLL_CTRL_SFTRST 0x80000000
HW_REGISTER_RO(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x30)
#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
HW_REGISTER_INDEXED(HW_ICOLL_PRIORITYn, REGS_ICOLL_BASE, 0x60, 0x10)
#define HW_ICOLL_PRIORITYn 0x60
#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */
#endif
arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
View file @ 3f52326a
/*
* STMP pinmux register definitions
* stmp37xx: PINCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -17,143 +18,71 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H
#define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H
#include <mach/stmp3xxx_regs.h>
#ifndef REGS_PINCTRL_BASE
#define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000)
#endif /* REGS_PINCTRL_BASE */
HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0)
#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100)
HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100)
#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110)
HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110)
#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120)
HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120)
#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130)
HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130)
#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000
#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140)
HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140)
#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0
#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300
#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150)
HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150)
#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160)
HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160)
#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170)
HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170)
HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200)
#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200)
HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210)
#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210)
HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220)
#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220)
HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230)
#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230)
HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240)
#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240)
HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250)
#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250)
HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260)
#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260)
HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270)
#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270)
HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280)
#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280)
HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290)
#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290)
HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0)
#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0)
HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0)
#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0)
HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0)
#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0)
HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0)
#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0)
HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0)
#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0)
HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300)
#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300)
#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002
#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004
#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008
#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010
#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000
HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310)
#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310)
#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000
#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000
#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000
#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000
#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000
HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320)
#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320)
HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330)
#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330)
#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400)
HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400)
#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410)
HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410)
#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420)
HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420)
#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500)
HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500)
#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510)
HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510)
#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520)
HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520)
#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600)
HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600)
#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610)
HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610)
#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620)
HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620)
HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700)
#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700)
HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710)
#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710)
HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720)
#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720)
HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800)
#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800)
HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810)
#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810)
HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820)
#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820)
HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900)
#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900)
HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910)
#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910)
HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920)
#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920)
HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00)
#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00)
HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10)
#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10)
HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20)
#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20)
HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00)
#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00)
HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10)
#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10)
HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20)
#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20)
#endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */
#ifndef _MACH_REGS_PINCTRL
#define _MACH_REGS_PINCTRL
#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
#define HW_PINCTRL_MUXSEL0 0x100
#define HW_PINCTRL_MUXSEL1 0x110
#define HW_PINCTRL_MUXSEL2 0x120
#define HW_PINCTRL_MUXSEL3 0x130
#define HW_PINCTRL_MUXSEL4 0x140
#define HW_PINCTRL_MUXSEL5 0x150
#define HW_PINCTRL_MUXSEL6 0x160
#define HW_PINCTRL_MUXSEL7 0x170
#define HW_PINCTRL_DRIVE0 0x200
#define HW_PINCTRL_DRIVE1 0x210
#define HW_PINCTRL_DRIVE2 0x220
#define HW_PINCTRL_DRIVE3 0x230
#define HW_PINCTRL_DRIVE4 0x240
#define HW_PINCTRL_DRIVE5 0x250
#define HW_PINCTRL_DRIVE6 0x260
#define HW_PINCTRL_DRIVE7 0x270
#define HW_PINCTRL_DRIVE8 0x280
#define HW_PINCTRL_DRIVE9 0x290
#define HW_PINCTRL_DRIVE10 0x2A0
#define HW_PINCTRL_DRIVE11 0x2B0
#define HW_PINCTRL_DRIVE12 0x2C0
#define HW_PINCTRL_DRIVE13 0x2D0
#define HW_PINCTRL_DRIVE14 0x2E0
#define HW_PINCTRL_PULL0 0x300
#define HW_PINCTRL_PULL1 0x310
#define HW_PINCTRL_PULL2 0x320
#define HW_PINCTRL_PULL3 0x330
#define HW_PINCTRL_DOUT0 0x400
#define HW_PINCTRL_DOUT1 0x410
#define HW_PINCTRL_DOUT2 0x420
#define HW_PINCTRL_DIN0 0x500
#define HW_PINCTRL_DIN1 0x510
#define HW_PINCTRL_DIN2 0x520
#define HW_PINCTRL_DOE0 0x600
#define HW_PINCTRL_DOE1 0x610
#define HW_PINCTRL_DOE2 0x620
#define HW_PINCTRL_PIN2IRQ0 0x700
#define HW_PINCTRL_PIN2IRQ1 0x710
#define HW_PINCTRL_PIN2IRQ2 0x720
#define HW_PINCTRL_IRQEN0 0x800
#define HW_PINCTRL_IRQEN1 0x810
#define HW_PINCTRL_IRQEN2 0x820
#define HW_PINCTRL_IRQLEVEL0 0x900
#define HW_PINCTRL_IRQLEVEL1 0x910
#define HW_PINCTRL_IRQLEVEL2 0x920
#define HW_PINCTRL_IRQPOL0 0xA00
#define HW_PINCTRL_IRQPOL1 0xA10
#define HW_PINCTRL_IRQPOL2 0xA20
#define HW_PINCTRL_IRQSTAT0 0xB00
#define HW_PINCTRL_IRQSTAT1 0xB10
#define HW_PINCTRL_IRQSTAT2 0xB20
#endif
arch/arm/mach-stmp37xx/include/mach/regs-power.h
View file @ 3f52326a
/*
* STMP POWER Register Definitions
* stmp37xx: POWER register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -17,15 +18,39 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_POWER
#define _MACH_REGS_POWER
#ifndef __ARCH_ARM___POWER_H
#define __ARCH_ARM___POWER_H 1
#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
#include <mach/stmp3xxx_regs.h>
#define HW_POWER_CTRL 0x0
#define BM_POWER_CTRL_CLKGATE 0x40000000
#define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000)
#define REGS_POWER_BASE_PHYS (0x80044000)
#define REGS_POWER_SIZE 0x00002000
HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020)
HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030)
#endif /* __ARCH_ARM___POWER_H */
#define HW_POWER_5VCTRL 0x10
#define HW_POWER_MINPWR 0x20
#define HW_POWER_CHARGE 0x30
#define HW_POWER_VDDDCTRL 0x40
#define HW_POWER_VDDACTRL 0x50
#define HW_POWER_VDDIOCTRL 0x60
#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
#define BP_POWER_VDDIOCTRL_TRG 0
#define HW_POWER_STS 0xB0
#define BM_POWER_STS_VBUSVALID 0x00000002
#define BM_POWER_STS_BVALID 0x00000004
#define BM_POWER_STS_AVALID 0x00000008
#define BM_POWER_STS_DC_OK 0x00000100
#define HW_POWER_RESET 0xE0
#define HW_POWER_DEBUG 0xF0
#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
#endif
arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
View file @ 3f52326a
/*
* include/asm-arm/arch-stmp3xxx/regstimer.h
* stmp37xx: TIMROT register definitions
*
* Copyright (c) 2008 SigmaTel Inc
* Copyright (c) 2008 Embedded Alley Solutions, Inc
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -16,37 +16,34 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ARCH_ARM_REGS_TIMROT_H
#define __ARCH_ARM_REGS_TIMROT_H
#ifndef _MACH_REGS_TIMROT
#define _MACH_REGS_TIMROT
#include <mach/stmp3xxx_regs.h>
#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
#define REGS_TIMROT_BASE (REGS_BASE + 0x00068000)
#define HW_TIMROT_ROTCTRL 0x0
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0)
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x20, 0x20)
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
#define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \
(((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
#define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & BM_TIMROT_TIMCTRLn_RELOAD)
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
#define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & BM_TIMROT_TIMCTRLn_UPDATE)
#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
#define BF_TIMROT_TIMCTRLn_POLARITY(v) \
(((v) << 8) & BM_TIMROT_TIMCTRLn_POLARITY)
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
#define BF_TIMROT_TIMCTRLn_IRQ_EN(v) \
(((v) << 14) & BM_TIMROT_TIMCTRLn_IRQ_EN)
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
#define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & BM_TIMROT_TIMCTRLn_IRQ)
HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x30, 0x20)
#define HW_TIMROT_TIMCTRLn 0x20
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
#define BP_TIMROT_TIMCTRLn_SELECT 0
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
#endif /* __ARCH_ARM_REGSTIMER_H */
#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
#define HW_TIMROT_TIMCOUNTn 0x30
#endif
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