Commit 3fbff9c8 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull 64-bit ARM SoC updates from Olof Johansson:
 "Changes to platform code for 64-bit ARM platforms.

  Nearly all of these are defconfig updates to enable new drivers or old
  drivers still used on these 64-bit platforms.

  Added platforms for this release are:

   - Broadcom BCM2837
   - Renesas R8A7796"

* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  arm64: remove duplicate PWM entry in defconfig
  arm64: Update default configuration
  arm64: defconfig: Enable more IP blocks for Exynos7 and Exynos5433
  arm64: amlogic: select gxbb clk driver
  arm64: defconfig: Enable S2MPS11 clock and S3C RTC driver
  arm64: marvell: enable Armada 3700 clock drivers
  arm64: defconfig: enable msm8996 pinctrl support
  arm64: defconfig: Enable qcom msm8996 clk drivers
  arm: defconfig: Enable PM8941 pwr key
  arm64: defconfig: enable stmmac and realtek PHY as modules
  arm64: Kconfig: select PM{,_GENERIC_DOMAINS} for ARCH_VEXPRESS
  arm64: defconfig: enable SENSORS_ARM_SCPI
  arm64: defconfig: enable Generic on-chip SRAM driver
  arm64: configs: enable PCIe driver for Armada 7K/8K
  arm64: Add platform selection for BCM2835.
  arm64: defconfig: disable plain NEON implementation of AES
  arm64: Allow for different DMA and CPU bus offsets
  arm64: defconfig: enable Renesas R8A7796 SoC
  arm64: defconfig: Enable Cadence MACB/GEM support
  ARM64: Kconfig: Select the Amlogic Meson pin controller driver
  ...
parents fbae5cbb 7e03e116
...@@ -13,6 +13,19 @@ config ARCH_ALPINE ...@@ -13,6 +13,19 @@ config ARCH_ALPINE
This enables support for the Annapurna Labs Alpine This enables support for the Annapurna Labs Alpine
Soc family. Soc family.
config ARCH_BCM2835
bool "Broadcom BCM2835 family"
select ARCH_REQUIRE_GPIOLIB
select CLKSRC_OF
select PINCTRL
select PINCTRL_BCM2835
select ARM_AMBA
select ARM_TIMER_SP804
select HAVE_ARM_ARCH_TIMER
help
This enables support for the Broadcom BCM2837 SoC.
This SoC is used in the Raspberry Pi 3 device.
config ARCH_BCM_IPROC config ARCH_BCM_IPROC
bool "Broadcom iProc SoC Family" bool "Broadcom iProc SoC Family"
select COMMON_CLK_IPROC select COMMON_CLK_IPROC
...@@ -36,6 +49,7 @@ config ARCH_EXYNOS ...@@ -36,6 +49,7 @@ config ARCH_EXYNOS
select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select SOC_SAMSUNG
help help
This enables support for ARMv8 based Samsung Exynos SoC family. This enables support for ARMv8 based Samsung Exynos SoC family.
...@@ -66,6 +80,10 @@ config ARCH_MEDIATEK ...@@ -66,6 +80,10 @@ config ARCH_MEDIATEK
config ARCH_MESON config ARCH_MESON
bool "Amlogic Platforms" bool "Amlogic Platforms"
select PINCTRL
select PINCTRL_MESON
select COMMON_CLK_AMLOGIC
select COMMON_CLK_GXBB
help help
This enables support for the Amlogic S905 SoCs. This enables support for the Amlogic S905 SoCs.
...@@ -73,6 +91,7 @@ config ARCH_MVEBU ...@@ -73,6 +91,7 @@ config ARCH_MVEBU
bool "Marvell EBU SoC Family" bool "Marvell EBU SoC Family"
select ARMADA_AP806_SYSCON select ARMADA_AP806_SYSCON
select ARMADA_CP110_SYSCON select ARMADA_CP110_SYSCON
select ARMADA_37XX_CLK
select MVEBU_ODMI select MVEBU_ODMI
help help
This enables support for Marvell EBU familly, including: This enables support for Marvell EBU familly, including:
...@@ -160,6 +179,8 @@ config ARCH_VEXPRESS ...@@ -160,6 +179,8 @@ config ARCH_VEXPRESS
bool "ARMv8 software model (Versatile Express)" bool "ARMv8 software model (Versatile Express)"
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK_VERSATILE select COMMON_CLK_VERSATILE
select PM
select PM_GENERIC_DOMAINS
select POWER_RESET_VEXPRESS select POWER_RESET_VEXPRESS
select VEXPRESS_CONFIG select VEXPRESS_CONFIG
help help
...@@ -168,6 +189,7 @@ config ARCH_VEXPRESS ...@@ -168,6 +189,7 @@ config ARCH_VEXPRESS
config ARCH_VULCAN config ARCH_VULCAN
bool "Broadcom Vulcan SOC Family" bool "Broadcom Vulcan SOC Family"
select GPIOLIB
help help
This enables support for Broadcom Vulcan SoC Family This enables support for Broadcom Vulcan SoC Family
......
...@@ -45,6 +45,7 @@ CONFIG_ARCH_ROCKCHIP=y ...@@ -45,6 +45,7 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_RENESAS=y CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7795=y
CONFIG_ARCH_R8A7796=y
CONFIG_ARCH_STRATIX10=y CONFIG_ARCH_STRATIX10=y
CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_SPRD=y CONFIG_ARCH_SPRD=y
...@@ -63,6 +64,7 @@ CONFIG_PCI_XGENE=y ...@@ -63,6 +64,7 @@ CONFIG_PCI_XGENE=y
CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y CONFIG_PCI_HISI=y
CONFIG_PCIE_QCOM=y CONFIG_PCIE_QCOM=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y CONFIG_SCHED_MC=y
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
...@@ -102,6 +104,7 @@ CONFIG_MTD_M25P80=y ...@@ -102,6 +104,7 @@ CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y CONFIG_VIRTIO_BLK=y
CONFIG_SRAM=y
# CONFIG_SCSI_PROC_FS is not set # CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_LOWLEVEL is not set
...@@ -121,6 +124,7 @@ CONFIG_TUN=y ...@@ -121,6 +124,7 @@ CONFIG_TUN=y
CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_NET=y
CONFIG_AMD_XGBE=y CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y CONFIG_NET_XGENE=y
CONFIG_MACB=y
CONFIG_E1000E=y CONFIG_E1000E=y
CONFIG_IGB=y CONFIG_IGB=y
CONFIG_IGBVF=y CONFIG_IGBVF=y
...@@ -128,6 +132,8 @@ CONFIG_SKY2=y ...@@ -128,6 +132,8 @@ CONFIG_SKY2=y
CONFIG_RAVB=y CONFIG_RAVB=y
CONFIG_SMC91X=y CONFIG_SMC91X=y
CONFIG_SMSC911X=y CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=m
CONFIG_REALTEK_PHY=m
CONFIG_MICREL_PHY=y CONFIG_MICREL_PHY=y
CONFIG_USB_PEGASUS=m CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m CONFIG_USB_RTL8150=m
...@@ -143,6 +149,8 @@ CONFIG_WL18XX=m ...@@ -143,6 +149,8 @@ CONFIG_WL18XX=m
CONFIG_WLCORE_SDIO=m CONFIG_WLCORE_SDIO=m
CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_PM8941_PWRKEY=y
# CONFIG_SERIO_SERPORT is not set # CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_AMBAKMI=y CONFIG_SERIO_AMBAKMI=y
CONFIG_LEGACY_PTY_COUNT=16 CONFIG_LEGACY_PTY_COUNT=16
...@@ -179,41 +187,62 @@ CONFIG_I2C_QUP=y ...@@ -179,41 +187,62 @@ CONFIG_I2C_QUP=y
CONFIG_I2C_TEGRA=y CONFIG_I2C_TEGRA=y
CONFIG_I2C_UNIPHIER_F=y CONFIG_I2C_UNIPHIER_F=y
CONFIG_I2C_RCAR=y CONFIG_I2C_RCAR=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SPI=y CONFIG_SPI=y
CONFIG_SPI_ORION=y CONFIG_SPI_ORION=y
CONFIG_SPI_PL022=y CONFIG_SPI_PL022=y
CONFIG_SPI_QUP=y CONFIG_SPI_QUP=y
CONFIG_SPI_SPIDEV=m CONFIG_SPI_SPIDEV=m
CONFIG_SPI_S3C64XX=y
CONFIG_SPMI=y CONFIG_SPMI=y
CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PL061=y CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y CONFIG_GPIO_RCAR=y
CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_MAX77620=y
CONFIG_POWER_RESET_MSM=y CONFIG_POWER_RESET_MSM=y
CONFIG_BATTERY_BQ27XXX=y
CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON=y
CONFIG_SENSORS_LM90=m CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA2XX=m
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_THERMAL=y CONFIG_THERMAL=y
CONFIG_THERMAL_EMULATION=y CONFIG_THERMAL_EMULATION=y
CONFIG_EXYNOS_THERMAL=y CONFIG_EXYNOS_THERMAL=y
CONFIG_WATCHDOG=y CONFIG_WATCHDOG=y
CONFIG_RENESAS_WDT=y CONFIG_RENESAS_WDT=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_MFD_MAX77620=y
CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_HI655X_PMIC=y CONFIG_MFD_HI655X_PMIC=y
CONFIG_REGULATOR=y CONFIG_REGULATOR=y
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_I2C=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_HI655X=y
CONFIG_REGULATOR_MAX77620=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SMD_RPM=y
CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_QCOM_SPMI=y
CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S2MPS11=y
CONFIG_DRM=m
CONFIG_DRM_NOUVEAU=m
CONFIG_DRM_TEGRA=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_FB=y CONFIG_FB=y
CONFIG_FB_ARMCLCD=y CONFIG_FB_ARMCLCD=y
CONFIG_BACKLIGHT_GENERIC=m
CONFIG_BACKLIGHT_LP855X=m
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_MONO is not set
...@@ -222,18 +251,23 @@ CONFIG_SOUND=y ...@@ -222,18 +251,23 @@ CONFIG_SOUND=y
CONFIG_SND=y CONFIG_SND=y
CONFIG_SND_SOC=y CONFIG_SND_SOC=y
CONFIG_SND_SOC_RCAR=y CONFIG_SND_SOC_RCAR=y
CONFIG_SND_SOC_SAMSUNG=y
CONFIG_SND_SOC_AK4613=y CONFIG_SND_SOC_AK4613=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_OTG=y CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_RCAR=y CONFIG_USB_XHCI_RCAR=y
CONFIG_USB_EHCI_EXYNOS=y
CONFIG_USB_XHCI_TEGRA=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MSM=y CONFIG_USB_EHCI_MSM=y
CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_EXYNOS=y
CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_DWC2=y CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_CHIPIDEA_HOST=y
...@@ -263,12 +297,15 @@ CONFIG_LEDS_TRIGGERS=y ...@@ -263,12 +297,15 @@ CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MAX77686=y
CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_TEGRA=y
CONFIG_RTC_DRV_XGENE=y CONFIG_RTC_DRV_XGENE=y
CONFIG_RTC_DRV_S3C=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y CONFIG_PL330_DMA=y
CONFIG_TEGRA20_APB_DMA=y CONFIG_TEGRA20_APB_DMA=y
...@@ -283,9 +320,11 @@ CONFIG_XEN_GNTDEV=y ...@@ -283,9 +320,11 @@ CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_SCPI=y
CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_CLK_QORIQ=y CONFIG_CLK_QORIQ=y
CONFIG_COMMON_CLK_QCOM=y CONFIG_COMMON_CLK_QCOM=y
CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8916=y
CONFIG_MSM_MMCC_8996=y
CONFIG_HWSPINLOCK_QCOM=y CONFIG_HWSPINLOCK_QCOM=y
CONFIG_MAILBOX=y CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y CONFIG_ARM_MHU=y
...@@ -297,12 +336,18 @@ CONFIG_QCOM_SMD_RPM=y ...@@ -297,12 +336,18 @@ CONFIG_QCOM_SMD_RPM=y
CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_132_SOC=y
CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y
CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USB_GPIO=y
CONFIG_PWM=y
CONFIG_PWM_TEGRA=m
CONFIG_COMMON_RESET_HI6220=y CONFIG_COMMON_RESET_HI6220=y
CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_HI6220_USB=y CONFIG_PHY_HI6220_USB=y
CONFIG_PHY_XGENE=y CONFIG_PHY_XGENE=y
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ACPI=y CONFIG_ACPI=y
CONFIG_IIO=y
CONFIG_EXYNOS_ADC=y
CONFIG_PWM_SAMSUNG=y
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
CONFIG_FANOTIFY=y CONFIG_FANOTIFY=y
...@@ -319,6 +364,8 @@ CONFIG_EFIVAR_FS=y ...@@ -319,6 +364,8 @@ CONFIG_EFIVAR_FS=y
CONFIG_SQUASHFS=y CONFIG_SQUASHFS=y
CONFIG_NFS_FS=y CONFIG_NFS_FS=y
CONFIG_NFS_V4=y CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y CONFIG_ROOT_NFS=y
CONFIG_9P_FS=y CONFIG_9P_FS=y
CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_437=y
...@@ -344,5 +391,5 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y ...@@ -344,5 +391,5 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y # CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
CONFIG_CRYPTO_CRC32_ARM64=y CONFIG_CRYPTO_CRC32_ARM64=y
...@@ -66,12 +66,16 @@ static inline bool is_device_dma_coherent(struct device *dev) ...@@ -66,12 +66,16 @@ static inline bool is_device_dma_coherent(struct device *dev)
static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{ {
return (dma_addr_t)paddr; dma_addr_t dev_addr = (dma_addr_t)paddr;
return dev_addr - ((dma_addr_t)dev->dma_pfn_offset << PAGE_SHIFT);
} }
static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr) static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
{ {
return (phys_addr_t)dev_addr; phys_addr_t paddr = (phys_addr_t)dev_addr;
return paddr + ((phys_addr_t)dev->dma_pfn_offset << PAGE_SHIFT);
} }
static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
...@@ -86,5 +90,14 @@ static inline void dma_mark_clean(void *addr, size_t size) ...@@ -86,5 +90,14 @@ static inline void dma_mark_clean(void *addr, size_t size)
{ {
} }
/* Override for dma_max_pfn() */
static inline unsigned long dma_max_pfn(struct device *dev)
{
dma_addr_t dma_max = (dma_addr_t)*dev->dma_mask;
return (ulong)dma_to_phys(dev, dma_max) >> PAGE_SHIFT;
}
#define dma_max_pfn(dev) dma_max_pfn(dev)
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
#endif /* __ASM_DMA_MAPPING_H */ #endif /* __ASM_DMA_MAPPING_H */
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