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Commit 40702432 authored by Hartley Sweeten's avatar Hartley Sweeten Committed by Russell King
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[ARM] 5528/1: ep93xx: add defines for dma clock magic numbers 

Update the dma clocks so that the magic numbers are named.

All the dma clocks have an enable bit to turn them on/off as
needed.  Currently these bits are in the code as "magic"
numbers.  This changes all of them to named defines to
improve code readability.

Also, the EP93XX_SYSCON_CLOCK_CONTROL register is improperly
named.  In the EP93xx User's Guide this register is called
PwrCnt (Power Control).  All of the uses of this register
are associated with the clock support so this patch also
modifies the names to match the User's Guide.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 68ee3d83
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Showing with 42 additions and 29 deletions
arch/arm/mach-ep93xx/clock.c
View file @ 40702432
...@@ -37,58 +37,58 @@ static struct clk clk_h; ...@@ -37,58 +37,58 @@ static struct clk clk_h;
static struct clk clk_p; static struct clk clk_p;
static struct clk clk_pll2; static struct clk clk_pll2;
static struct clk clk_usb_host = { static struct clk clk_usb_host = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
}; };
/* DMA Clocks */ /* DMA Clocks */
static struct clk clk_m2p0 = { static struct clk clk_m2p0 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00020000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
}; };
static struct clk clk_m2p1 = { static struct clk clk_m2p1 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00010000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
}; };
static struct clk clk_m2p2 = { static struct clk clk_m2p2 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00080000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
}; };
static struct clk clk_m2p3 = { static struct clk clk_m2p3 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00040000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
}; };
static struct clk clk_m2p4 = { static struct clk clk_m2p4 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00200000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
}; };
static struct clk clk_m2p5 = { static struct clk clk_m2p5 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00100000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
}; };
static struct clk clk_m2p6 = { static struct clk clk_m2p6 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00800000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
}; };
static struct clk clk_m2p7 = { static struct clk clk_m2p7 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x00400000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
}; };
static struct clk clk_m2p8 = { static struct clk clk_m2p8 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x02000000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
}; };
static struct clk clk_m2p9 = { static struct clk clk_m2p9 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x01000000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
}; };
static struct clk clk_m2m0 = { static struct clk clk_m2m0 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x04000000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
}; };
static struct clk clk_m2m1 = { static struct clk clk_m2m1 = {
.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_reg = EP93XX_SYSCON_PWRCNT,
.enable_mask = 0x08000000, .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
}; };
#define INIT_CK(dev,con,ck) \ #define INIT_CK(dev,con,ck) \
......
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
View file @ 40702432
...@@ -152,9 +152,22 @@ ...@@ -152,9 +152,22 @@
#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) #define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000)
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 #define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 #define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
......
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