Commit 40c390c7 authored by Will Deacon's avatar Will Deacon

ARM: perf: don't pretend to support counting of L1I writes

ARM has a harvard cache architecture and cannot write directly to the
I-side.

This patch removes the L1I write events from the cache map (which
previously returned *read* events in many cases).
Reported-by: default avatarMike Williams <michael.williams@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 1764c591
...@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
...@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
......
...@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
...@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
...@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
/* /*
* The prefetch counters don't differentiate between the I * The prefetch counters don't differentiate between the I
...@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
...@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
......
...@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] ...@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
......
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