Commit 41190cd7 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher

drm/amdgpu: remove ih_info parameter of gfx_ras_late_init

gfx_ras_late_init can get the info by itself
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 56c54b25
...@@ -571,18 +571,16 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) ...@@ -571,18 +571,16 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
mutex_unlock(&adev->gfx.gfx_off_mutex); mutex_unlock(&adev->gfx.gfx_off_mutex);
} }
int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
void *ras_ih_info)
{ {
int r; int r;
struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
struct ras_fs_if fs_info = { struct ras_fs_if fs_info = {
.sysfs_name = "gfx_err_count", .sysfs_name = "gfx_err_count",
.debugfs_name = "gfx_err_inject", .debugfs_name = "gfx_err_inject",
}; };
struct ras_ih_if ih_info = {
if (!ih_info) .cb = amdgpu_gfx_process_ras_data_cb,
return -EINVAL; };
if (!adev->gfx.ras_if) { if (!adev->gfx.ras_if) {
adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
...@@ -593,10 +591,10 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, ...@@ -593,10 +591,10 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
adev->gfx.ras_if->sub_block_index = 0; adev->gfx.ras_if->sub_block_index = 0;
strcpy(adev->gfx.ras_if->name, "gfx"); strcpy(adev->gfx.ras_if->name, "gfx");
} }
fs_info.head = ih_info->head = *adev->gfx.ras_if; fs_info.head = ih_info.head = *adev->gfx.ras_if;
r = amdgpu_ras_late_init(adev, adev->gfx.ras_if, r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
&fs_info, ih_info); &fs_info, &ih_info);
if (r) if (r)
goto free; goto free;
...@@ -612,7 +610,7 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, ...@@ -612,7 +610,7 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
return 0; return 0;
late_fini: late_fini:
amdgpu_ras_late_fini(adev, adev->gfx.ras_if, ih_info); amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
free: free:
kfree(adev->gfx.ras_if); kfree(adev->gfx.ras_if);
adev->gfx.ras_if = NULL; adev->gfx.ras_if = NULL;
......
...@@ -358,8 +358,7 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, ...@@ -358,8 +358,7 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
int pipe, int queue); int pipe, int queue);
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
void *ras_ih_info);
void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
void *err_data, void *err_data,
......
...@@ -4194,12 +4194,9 @@ static int gfx_v9_0_early_init(void *handle) ...@@ -4194,12 +4194,9 @@ static int gfx_v9_0_early_init(void *handle)
static int gfx_v9_0_ecc_late_init(void *handle) static int gfx_v9_0_ecc_late_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct ras_ih_if ih_info = {
.cb = amdgpu_gfx_process_ras_data_cb,
};
int r; int r;
r = amdgpu_gfx_ras_late_init(adev, &ih_info); r = amdgpu_gfx_ras_late_init(adev);
if (r) if (r)
return r; return r;
......
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