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Commit 43a1839c authored by Paul Mundt's avatar Paul Mundt
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sh: SH7786 clock framework rewrite. 

This rewrites the SH7786 clock framework support completely. It's
reworked to provide all of the DIV4 and MSTP function clocks. This brings
it in line with the current clock framework code and lets us drop SH7786
from the list of CPUs that require legacy CPG handling.
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent a4ae2b2b
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Showing with 91 additions and 99 deletions
arch/sh/Kconfig
View file @ 43a1839c
......@@ -551,8 +551,7 @@ config SH_PCLK_FREQ
CPU_SUBTYPE_SH7203 || \
CPU_SUBTYPE_SH7206 || \
CPU_SUBTYPE_SH7263 || \
CPU_SUBTYPE_MXG || \
CPU_SUBTYPE_SH7786
CPU_SUBTYPE_MXG
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
default "66000000" if CPU_SUBTYPE_SH4_202
default "50000000"
......@@ -566,7 +565,8 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
!CPU_SUBTYPE_SH7786
config SH_CLK_MD
int "CPU Mode Pin Setting"
......
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
View file @ 43a1839c
......@@ -3,11 +3,7 @@
*
* SH7786 support for the clock framework
*
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* Based on SH7785
* Copyright (C) 2007 Paul Mundt
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
......@@ -15,127 +11,123 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
static int ifc_divisors[] = { 1, 2, 4, 1 };
static int sfc_divisors[] = { 1, 1, 4, 1 };
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
24, 32, 1, 1, 1, 1, 1, 1 };
static int mfc_divisors[] = { 1, 1, 4, 1 };
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
24, 32, 1, 48, 1, 1, 1, 1 };
static void master_clk_init(struct clk *clk)
{
clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
}
static struct clk_ops sh7786_master_clk_ops = {
.init = master_clk_init,
/*
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
static struct clk extal_clk = {
.name = "extal",
.id = -1,
.rate = 33333333,
};
static unsigned long module_clk_recalc(struct clk *clk)
static unsigned long pll_recalc(struct clk *clk)
{
int idx = (ctrl_inl(FRQMR1) & 0x000f);
return clk->parent->rate / pfc_divisors[idx];
}
int multiplier;
static struct clk_ops sh7786_module_clk_ops = {
.recalc = module_clk_recalc,
};
/*
* Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
* while modes 3, 4, and 5 use an x32.
*/
multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
return clk->parent->rate / bfc_divisors[idx];
return clk->parent->rate * multiplier;
}
static struct clk_ops sh7786_bus_clk_ops = {
.recalc = bus_clk_recalc,
static struct clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7786_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
static struct clk pll_clk = {
.name = "pll_clk",
.id = -1,
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static struct clk_ops *sh7786_clk_ops[] = {
&sh7786_master_clk_ops,
&sh7786_module_clk_ops,
&sh7786_bus_clk_ops,
&sh7786_cpu_clk_ops,
static struct clk *clks[] = {
&extal_clk,
&pll_clk,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7786_clk_ops))
*ops = sh7786_clk_ops[idx];
}
static unsigned long shyway_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
return clk->parent->rate / sfc_divisors[idx];
}
static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48 };
static struct clk_ops sh7786_shyway_clk_ops = {
.recalc = shyway_clk_recalc,
static struct clk_div_mult_table div4_table = {
.divisors = div2,
.nr_divisors = ARRAY_SIZE(div2),
};
static struct clk sh7786_shyway_clk = {
.name = "shyway_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh7786_shyway_clk_ops,
};
enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
static unsigned long ddr_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
return clk->parent->rate / mfc_divisors[idx];
}
#define DIV4(_str, _bit, _mask, _flags) \
SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
static struct clk_ops sh7786_ddr_clk_ops = {
.recalc = ddr_clk_recalc,
struct clk div4_clks[DIV4_NR] = {
[DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
[DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
[DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
[DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
[DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
};
static struct clk sh7786_ddr_clk = {
.name = "ddr_clk",
.flags = CLK_ENABLE_ON_INIT,
.ops = &sh7786_ddr_clk_ops,
};
/*
* Additional SH7786-specific on-chip clocks that aren't already part of the
* clock framework
*/
static struct clk *sh7786_onchip_clocks[] = {
&sh7786_shyway_clk,
&sh7786_ddr_clk,
#define MSTPCR0 0xffc40030
#define MSTPCR1 0xffc40034
static struct clk mstp_clks[] = {
/* MSTPCR0 */
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
/* MSTPCR1 */
SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
};
int __init arch_clk_init(void)
{
struct clk *clk;
int i, ret = 0;
cpg_clk_init();
clk = clk_get(NULL, "master_clk");
for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
struct clk *clkp = sh7786_onchip_clocks[i];
clkp->parent = clk;
ret |= clk_register(clkp);
}
for (i = 0; i < ARRAY_SIZE(clks); i++)
ret |= clk_register(clks[i]);
clk_put(clk);
if (!ret)
ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
&div4_table);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
return ret;
}
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