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Commit 44197797 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull Devicetree updates from Rob Herring:

 - Improve device links cycle detection and breaking. Add more bindings
   for device link dependencies.

 - Refactor parsing 'no-map' in __reserved_mem_alloc_size()

 - Improve DT unittest 'ranges' and 'dma-ranges' test case to check
   differing cell sizes

 - Various http to https link conversions

 - Add a schema check to prevent 'syscon' from being used by itself
   without a more specific compatible

 - A bunch more DT binding conversions to schema

* tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
  of: reserved-memory: remove duplicated call to of_get_flat_dt_prop() for no-map node
  of: unittest: Use bigger address cells to catch parser regressions
  dt-bindings: memory-controllers: Convert mmdc to json-schema
  dt-bindings: mtd: Convert imx nand to json-schema
  dt-bindings: mtd: Convert gpmi nand to json-schema
  dt-bindings: iio: io-channel-mux: Fix compatible string in example code
  of: property: Add device link support for pinctrl-0 through pinctrl-8
  of: property: Add device link support for multiple DT bindings
  dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema
  dt-bindings: mux: mux.h: drop a duplicated word
  dt-bindings: misc: Convert olpc,xo1.75-ec to json-schema
  dt-bindings: aspeed-lpc: Replace HTTP links with HTTPS ones
  dt-bindings: drm/bridge: Replace HTTP links with HTTPS ones
  drm/tilcdc: Replace HTTP links with HTTPS ones
  dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support
  dt-bindings: fpga: Replace HTTP links with HTTPS ones
  dt-bindings: virtio: Replace HTTP links with HTTPS ones
  dt-bindings: media: imx274: Add optional input clock and supplies
  dt-bindings: i2c-gpio: Use 'deprecated' keyword on deprecated properties
  dt-bindings: interrupt-controller: Fix typos in loongson,liointc.yaml
  ...
parents 1d8ce0e0 6f1188b4
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Documentation/devicetree/bindings/clock/imx35-clock.yaml
View file @ 44197797
......@@ -130,7 +130,7 @@ examples:
#clock-cells = <1>;
};
esdhc@53fb4000 {
mmc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
......
Documentation/devicetree/bindings/clock/imx7ulp-clock.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Clock bindings for Freescale i.MX7ULP
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this binding doc is only for A7 clock domain.
System Clock Generation (SCG) modules:
---------------------------------------------------------------------
The System Clock Generation (SCG) is responsible for clock generation
and distribution across this device. Functions performed by the SCG
include: clock reference selection, generation of clock used to derive
processor, system, peripheral bus and external memory interface clocks,
source selection for peripheral clocks and control of power saving
clock gating mode.
Required properties:
- compatible: Should be "fsl,imx7ulp-scg1".
- reg : Should contain registers location and length.
- #clock-cells: Should be <1>.
- clocks: Should contain the fixed input clocks.
- clock-names: Should contain the following clock names:
"rosc", "sosc", "sirc", "firc", "upll", "mpll".
Peripheral Clock Control (PCC) modules:
---------------------------------------------------------------------
The Peripheral Clock Control (PCC) is responsible for clock selection,
optional division and clock gating mode for peripherals in their
respected power domain
Required properties:
- compatible: Should be one of:
"fsl,imx7ulp-pcc2",
"fsl,imx7ulp-pcc3".
- reg : Should contain registers location and length.
- #clock-cells: Should be <1>.
- clocks: Should contain the fixed input clocks.
- clock-names: Should contain the following clock names:
"nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
"apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
"mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See include/dt-bindings/clock/imx7ulp-clock.h
for the full list of i.MX7ULP clock IDs of each module.
Examples:
#include <dt-bindings/clock/imx7ulp-clock.h>
scg1: scg1@403e0000 {
compatible = "fsl,imx7ulp-scg1;
reg = <0x403e0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&sirc>,
<&firc>, <&upll>, <&mpll>;
clock-names = "rosc", "sosc", "sirc",
"firc", "upll", "mpll";
#clock-cells = <1>;
};
pcc2: pcc2@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
#clock-cells = <1>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&scg1 IMX7ULP_CLK_DDR_DIV>,
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
"upll", "sosc_bus_clk", "mpll",
"firc_bus_clk", "rosc", "spll_bus_clk";
};
usdhc1: usdhc@40380000 {
compatible = "fsl,imx7ulp-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names ="ipg", "ahb", "per";
bus-width = <4>;
};
Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
maintainers:
- A.s. Dong <aisheng.dong@nxp.com>
description: |
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this binding doc is only for A7 clock domain.
The Peripheral Clock Control (PCC) is responsible for clock selection,
optional division and clock gating mode for peripherals in their
respected power domain.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
i.MX7ULP clock IDs of each module.
properties:
compatible:
enum:
- fsl,imx7ulp-pcc2
- fsl,imx7ulp-pcc3
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
items:
- description: nic1 bus clock
- description: nic1 clock
- description: ddr clock
- description: apll pfd2
- description: apll pfd1
- description: apll pfd0
- description: usb pll
- description: system osc bus clock
- description: fast internal reference clock bus
- description: rtc osc
- description: system pll bus clock
clock-names:
items:
- const: nic1_bus_clk
- const: nic1_clk
- const: ddr_clk
- const: apll_pfd2
- const: apll_pfd1
- const: apll_pfd0
- const: upll
- const: sosc_bus_clk
- const: firc_bus_clk
- const: rosc
- const: spll_bus_clk
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
#clock-cells = <1>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&scg1 IMX7ULP_CLK_DDR_DIV>,
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
"upll", "sosc_bus_clk", "firc_bus_clk",
"rosc", "spll_bus_clk";
};
mmc@40380000 {
compatible = "fsl,imx7ulp-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names ="ipg", "ahb", "per";
bus-width = <4>;
};
Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
maintainers:
- A.s. Dong <aisheng.dong@nxp.com>
description: |
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this binding doc is only for A7 clock domain.
The System Clock Generation (SCG) is responsible for clock generation
and distribution across this device. Functions performed by the SCG
include: clock reference selection, generation of clock used to derive
processor, system, peripheral bus and external memory interface clocks,
source selection for peripheral clocks and control of power saving
clock gating mode.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
i.MX7ULP clock IDs of each module.
properties:
compatible:
const: fsl,imx7ulp-scg1
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
items:
- description: rtc osc
- description: system osc
- description: slow internal reference clock
- description: fast internal reference clock
- description: usb PLL
clock-names:
items:
- const: rosc
- const: sosc
- const: sirc
- const: firc
- const: upll
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@403e0000 {
compatible = "fsl,imx7ulp-scg1";
reg = <0x403e0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&sirc>,
<&firc>, <&upll>;
clock-names = "rosc", "sosc", "sirc",
"firc", "upll";
#clock-cells = <1>;
};
mmc@40380000 {
compatible = "fsl,imx7ulp-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names ="ipg", "ahb", "per";
bus-width = <4>;
};
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
View file @ 44197797
......@@ -62,7 +62,7 @@ examples:
};
mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
compatible = "fsl,imx8qxp-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
......
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
View file @ 44197797
......@@ -2,7 +2,7 @@ SN65DSI86 DSI to eDP bridge chip
--------------------------------
This is the binding for Texas Instruments SN65DSI86 bridge.
http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
Required properties:
- compatible: Must be "ti,sn65dsi86"
......
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
View file @ 44197797
......@@ -46,7 +46,7 @@ Optional nodes:
crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
for Blue[3-7]. For more details see section 3.1.1 in AM335x
Silicon Errata:
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
Example:
......
Documentation/devicetree/bindings/fpga/fpga-region.txt
View file @ 44197797
......@@ -493,4 +493,4 @@ FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
--
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
Documentation/devicetree/bindings/gpio/mrvl-gpio.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Marvell PXA GPIO controller
Required properties:
- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
"intel,pxa27x-gpio", "intel,pxa3xx-gpio",
"marvell,pxa93x-gpio", "marvell,mmp-gpio",
"marvell,mmp2-gpio" or marvell,pxa1928-gpio.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all gpio pins.
There're three gpio interrupts in arch-pxa, and they're gpio0,
gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
gpio_mux.
- interrupt-names : Should be the names of irq resources. Each interrupt
uses its own interrupt name, so there should be as many interrupt names
as referenced interrupts.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify flags. See gpio.txt for possible
values.
Example for a MMP platform:
gpio: gpio@d4019000 {
compatible = "marvell,mmp-gpio";
reg = <0xd4019000 0x1000>;
interrupts = <49>;
interrupt-names = "gpio_mux";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
Example for a PXA3xx platform:
gpio: gpio@40e00000 {
compatible = "intel,pxa3xx-gpio";
reg = <0x40e00000 0x10000>;
interrupt-names = "gpio0", "gpio1", "gpio_mux";
interrupts = <8 9 10>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
Documentation/devicetree/bindings/gpio/mrvl-gpio.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell PXA GPIO controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Rob Herring <robh+dt@kernel.org>
allOf:
- if:
properties:
compatible:
contains:
enum:
- intel,pxa25x-gpio
- intel,pxa26x-gpio
- intel,pxa27x-gpio
- intel,pxa3xx-gpio
then:
properties:
interrupts:
minItems: 3
maxItems: 3
interrupt-names:
items:
- const: gpio0
- const: gpio1
- const: gpio_mux
- if:
properties:
compatible:
contains:
enum:
- marvell,mmp-gpio
- marvell,mmp2-gpio
then:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: gpio_mux
properties:
$nodename:
pattern: '^gpio@[0-9a-f]+$'
compatible:
enum:
- intel,pxa25x-gpio
- intel,pxa26x-gpio
- intel,pxa27x-gpio
- intel,pxa3xx-gpio
- marvell,mmp-gpio
- marvell,mmp2-gpio
- marvell,pxa93x-gpio
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
ranges: true
'#address-cells':
const: 1
'#size-cells':
const: 1
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
interrupts: true
interrupt-names: true
interrupt-controller: true
'#interrupt-cells':
const: 2
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
properties:
reg:
maxItems: 1
required:
- reg
additionalProperties: false
required:
- compatible
- '#address-cells'
- '#size-cells'
- reg
- gpio-controller
- '#gpio-cells'
- interrupts
- interrupt-names
- interrupt-controller
- '#interrupt-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/pxa-clock.h>
gpio@40e00000 {
compatible = "intel,pxa3xx-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40e00000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <8>, <9>, <10>;
interrupt-names = "gpio0", "gpio1", "gpio_mux";
clocks = <&clks CLK_GPIO>;
interrupt-controller;
#interrupt-cells = <2>;
};
- |
#include <dt-bindings/clock/marvell,pxa910.h>
gpio@d4019000 {
compatible = "marvell,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
clocks = <&soc_clocks PXA910_CLK_GPIO>;
resets = <&soc_clocks PXA910_CLK_GPIO>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
};
...
Documentation/devicetree/bindings/i2c/i2c-gpio.yaml
View file @ 44197797
......@@ -52,15 +52,15 @@ properties:
description: sda and scl gpio, alternative for {sda,scl}-gpios
i2c-gpio,sda-open-drain:
# Generate a warning if present
not: true
type: boolean
deprecated: true
description: this means that something outside of our control has put
the GPIO line used for SDA into open drain mode, and that something is
not the GPIO chip. It is essentially an inconsistency flag.
i2c-gpio,scl-open-drain:
# Generate a warning if present
not: true
type: boolean
deprecated: true
description: this means that something outside of our control has put the
GPIO line used for SCL into open drain mode, and that something is not
the GPIO chip. It is essentially an inconsistency flag.
......
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale Low Power Inter IC (LPI2C) for i.MX
Required properties:
- compatible :
- "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc
- "fsl,imx8qxp-lpi2c" for LPI2C compatible with the one integrated on i.MX8QXP soc
- "fsl,imx8qm-lpi2c" for LPI2C compatible with the one integrated on i.MX8QM soc
- reg : address and length of the lpi2c master registers
- interrupts : lpi2c interrupt
- clocks : lpi2c clock specifier
Examples:
lpi2c7: lpi2c7@40a50000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A50000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C7>;
};
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Low Power Inter IC (LPI2C) for i.MX
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
enum:
- fsl,imx7ulp-lpi2c
- fsl,imx8qxp-lpi2c
- fsl,imx8qm-lpi2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
lpi2c7@40a50000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A50000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C7>;
};
Documentation/devicetree/bindings/i2c/i2c-imx.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
Required properties:
- compatible :
- "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC
- "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC
- "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC
- reg : Should contain I2C/HS-I2C registers location and length
- interrupts : Should contain I2C/HS-I2C interrupt
- clocks : Should contain the I2C/HS-I2C clock specifier
Optional properties:
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
The absence of the property indicates the default frequency 100 kHz.
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
- scl-gpios: specify the gpio related to SCL pin
- sda-gpios: specify the gpio related to SDA pin
- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
bus recovery, call it "gpio" state
Examples:
i2c@83fc4000 { /* I2C2 on i.MX51 */
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
};
i2c@70038000 { /* HS-I2C on i.MX51 */
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x70038000 0x4000>;
interrupts = <64>;
clock-frequency = <400000>;
};
i2c0: i2c@40066000 { /* i2c0 on vf610 */
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts =<0 71 0x04>;
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx","tx";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
};
Documentation/devicetree/bindings/i2c/i2c-imx.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
maintainers:
- Wolfram Sang <wolfram@the-dreams.de>
properties:
compatible:
oneOf:
- const: fsl,imx1-i2c
- const: fsl,imx21-i2c
- const: fsl,vf610-i2c
- items:
- const: fsl,imx35-i2c
- const: fsl,imx1-i2c
- items:
- enum:
- fsl,imx25-i2c
- fsl,imx27-i2c
- fsl,imx31-i2c
- fsl,imx50-i2c
- fsl,imx51-i2c
- fsl,imx53-i2c
- fsl,imx6q-i2c
- fsl,imx6sl-i2c
- fsl,imx6sx-i2c
- fsl,imx6sll-i2c
- fsl,imx6ul-i2c
- fsl,imx7s-i2c
- fsl,imx8mq-i2c
- fsl,imx8mm-i2c
- fsl,imx8mn-i2c
- fsl,imx8mp-i2c
- const: fsl,imx21-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: ipg
clock-frequency:
enum: [ 100000, 400000 ]
dmas:
items:
- description: DMA controller phandle and request line for RX
- description: DMA controller phandle and request line for TX
dma-names:
items:
- const: rx
- const: tx
sda-gpios:
maxItems: 1
scl-gpios:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@83fc4000 {
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
};
i2c@40066000 {
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx", "tx";
};
Documentation/devicetree/bindings/i2c/i2c-mxs.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale MXS Inter IC (I2C) Controller
Required properties:
- compatible: Should be "fsl,<chip>-i2c"
- reg: Should contain registers location and length
- interrupts: Should contain ERROR interrupt number
- clock-frequency: Desired I2C bus clock frequency in Hz.
Only 100000Hz and 400000Hz modes are supported.
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and I2C DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Examples:
i2c0: i2c@80058000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-i2c";
reg = <0x80058000 2000>;
interrupts = <111>;
clock-frequency = <100000>;
dmas = <&dma_apbx 6>;
dma-names = "rx-tx";
};
Documentation/devicetree/bindings/i2c/i2c-mxs.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mxs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MXS Inter IC (I2C) Controller
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
properties:
compatible:
enum:
- fsl,imx23-i2c
- fsl,imx28-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-frequency:
enum: [ 100000, 400000 ]
dmas:
maxItems: 1
dma-names:
const: rx-tx
required:
- compatible
- reg
- interrupts
- dmas
- dma-names
additionalProperties: false
examples:
- |
i2c@80058000 {
compatible = "fsl,imx28-i2c";
reg = <0x80058000 2000>;
interrupts = <111>;
clock-frequency = <100000>;
dmas = <&dma_apbx 6>;
dma-names = "rx-tx";
};
Documentation/devicetree/bindings/i2c/i2c-pxa.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Marvell MMP I2C controller
Required properties :
- reg : Offset and length of the register set for the device
- compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
as shown in the example below.
For the Armada 3700, the compatible should be "marvell,armada-3700-i2c".
Recommended properties :
- interrupts : the interrupt number
- mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
status register of i2c controller instead.
- mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
Examples:
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
};
Documentation/devicetree/bindings/i2c/i2c-pxa.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP I2C controller bindings
maintainers:
- Rob Herring <robh+dt@kernel.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
not:
required:
- mrvl,i2c-polling
then:
required:
- interrupts
properties:
compatible:
enum:
- mrvl,mmp-twsi
- mrvl,pxa-i2c
- marvell,armada-3700-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
resets:
minItems: 1
mrvl,i2c-polling:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Disable interrupt of i2c controller. Polling status register of i2c
controller instead.
mrvl,i2c-fast-mode:
$ref: /schemas/types.yaml#/definitions/flag
description: Enable fast mode of i2c controller.
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- '#address-cells'
- '#size-cells'
examples:
- |
#include <dt-bindings/clock/marvell,mmp2.h>
i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
clocks = <&soc_clocks MMP2_CLK_TWSI1>;
mrvl,i2c-fast-mode;
#address-cells = <1>;
#size-cells = <0>;
};
...
Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt
View file @ 44197797
......@@ -21,7 +21,7 @@ controller state. The mux controller state is described in
Example:
mux: mux-controller {
compatible = "mux-gpio";
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
......
Documentation/devicetree/bindings/input/imx-keypad.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale i.MX Keypad Port(KPP) device tree bindings
The KPP is designed to interface with a keypad matrix with 2-point contact
or 3-point contact keys. The KPP is designed to simplify the software task
of scanning a keypad matrix. The KPP is capable of detecting, debouncing,
and decoding one or multiple keys pressed simultaneously on a keypad.
Required SoC Specific Properties:
- compatible: Should be "fsl,<soc>-kpp".
- reg: Physical base address of the KPP and length of memory mapped
region.
- interrupts: The KPP interrupt number to the CPU(s).
- clocks: The clock provided by the SoC to the KPP. Some SoCs use dummy
clock(The clock for the KPP is provided by the SoCs automatically).
Required Board Specific Properties:
- pinctrl-names: The definition can be found at
pinctrl/pinctrl-bindings.txt.
- pinctrl-0: The definition can be found at
pinctrl/pinctrl-bindings.txt.
- linux,keymap: The definition can be found at
bindings/input/matrix-keymap.txt.
Example:
kpp: kpp@73f94000 {
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
linux,keymap = <0x00000067 /* KEY_UP */
0x0001006c /* KEY_DOWN */
0x00020072 /* KEY_VOLUMEDOWN */
0x00030066 /* KEY_HOME */
0x0100006a /* KEY_RIGHT */
0x01010069 /* KEY_LEFT */
0x0102001c /* KEY_ENTER */
0x01030073 /* KEY_VOLUMEUP */
0x02000040 /* KEY_F6 */
0x02010042 /* KEY_F8 */
0x02020043 /* KEY_F9 */
0x02030044 /* KEY_F10 */
0x0300003b /* KEY_F1 */
0x0301003c /* KEY_F2 */
0x0302003d /* KEY_F3 */
0x03030074>; /* KEY_POWER */
};
Documentation/devicetree/bindings/input/imx-keypad.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/imx-keypad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX Keypad Port(KPP) device tree bindings
maintainers:
- Liu Ying <gnuiyl@gmail.com>
allOf:
- $ref: "/schemas/input/matrix-keymap.yaml#"
description: |
The KPP is designed to interface with a keypad matrix with 2-point contact
or 3-point contact keys. The KPP is designed to simplify the software task
of scanning a keypad matrix. The KPP is capable of detecting, debouncing,
and decoding one or multiple keys pressed simultaneously on a keypad.
properties:
compatible:
oneOf:
- const: fsl,imx21-kpp
- items:
- enum:
- fsl,imx25-kpp
- fsl,imx27-kpp
- fsl,imx31-kpp
- fsl,imx35-kpp
- fsl,imx51-kpp
- fsl,imx53-kpp
- fsl,imx50-kpp
- fsl,imx6q-kpp
- fsl,imx6sx-kpp
- fsl,imx6sl-kpp
- fsl,imx6sll-kpp
- fsl,imx6ul-kpp
- fsl,imx7d-kpp
- const: fsl,imx21-kpp
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- linux,keymap
unevaluatedProperties: false
examples:
- |
keypad@73f94000 {
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
linux,keymap = <0x00000067 /* KEY_UP */
0x0001006c /* KEY_DOWN */
0x00020072 /* KEY_VOLUMEDOWN */
0x00030066 /* KEY_HOME */
0x0100006a /* KEY_RIGHT */
0x01010069 /* KEY_LEFT */
0x0102001c /* KEY_ENTER */
0x01030073 /* KEY_VOLUMEUP */
0x02000040 /* KEY_F6 */
0x02010042 /* KEY_F8 */
0x02020043 /* KEY_F9 */
0x02030044 /* KEY_F10 */
0x0300003b /* KEY_F1 */
0x0301003c /* KEY_F2 */
0x0302003d /* KEY_F3 */
0x03030074>; /* KEY_POWER */
};
Documentation/devicetree/bindings/input/matrix-keymap.txt
View file @ 44197797
A simple common binding for matrix-connected key boards. Currently targeted at
defining the keys in the scope of linux key codes since that is a stable and
standardized interface at this time.
Required properties:
- linux,keymap: an array of packed 1-cell entries containing the equivalent
of row, column and linux key-code. The 32-bit big endian cell is packed
as:
row << 24 | column << 16 | key-code
Optional properties:
Properties for the number of rows and columns are optional because some
drivers will use fixed values for these.
- keypad,num-rows: Number of row lines connected to the keypad controller.
- keypad,num-columns: Number of column lines connected to the keypad
controller.
Some users of this binding might choose to specify secondary keymaps for
cases where there is a modifier key such as a Fn key. Proposed names
for said properties are "linux,fn-keymap" or with another descriptive
word for the modifier other from "Fn".
Example:
linux,keymap = < 0x00030012
0x0102003a >;
keypad,num-rows = <2>;
keypad,num-columns = <8>;
This file has been moved to matrix-keymap.yaml
Documentation/devicetree/bindings/input/matrix-keymap.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/matrix-keymap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common key matrices binding for matrix-connected key boards
maintainers:
- Olof Johansson <olof@lixom.net>
description: |
A simple common binding for matrix-connected key boards. Currently targeted at
defining the keys in the scope of linux key codes since that is a stable and
standardized interface at this time.
Some users of this binding might choose to specify secondary keymaps for
cases where there is a modifier key such as a Fn key. Proposed names
for said properties are "linux,fn-keymap" or with another descriptive
word for the modifier other from "Fn".
properties:
linux,keymap:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
description: |
An array of packed 1-cell entries containing the equivalent of row,
column and linux key-code. The 32-bit big endian cell is packed as:
row << 24 | column << 16 | key-code
keypad,num-rows:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of row lines connected to the keypad controller.
keypad,num-columns:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of column lines connected to the keypad controller.
examples:
- |
keypad {
/* ... */
linux,keymap = < 0x00030012
0x0102003a >;
keypad,num-rows = <2>;
keypad,num-columns = <8>;
};
Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
View file @ 44197797
......@@ -51,8 +51,8 @@ properties:
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
and each bit in the cell refers to a children interrupt fron 0 to 31.
If a CPU interrupt line didn't connected with liointc, then keep it's
and each bit in the cell refers to a child interrupt from 0 to 31.
If a CPU interrupt line didn't connect with liointc, then keep its
cell with zero.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 4
......
Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Marvell MMP Interrupt controller
Required properties:
- compatible : Should be
"mrvl,mmp-intc" on Marvel MMP,
"mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
"marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
- reg : Address and length of the register set of the interrupt controller.
If the interrupt controller is intc, address and length means the range
of the whole interrupt controller. The "marvell,mmp3-intc" controller
also has a secondary range for the second CPU core. If the interrupt
controller is mux-intc, address and length means one register. Since
address of mux-intc is in the range of intc. mux-intc is secondary
interrupt controller.
- reg-names : Name of the register set of the interrupt controller. It's
only required in mux-intc interrupt controller.
- interrupts : Should be the port interrupt shared by mux interrupts. It's
only required in mux-intc interrupt controller.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source.
- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
controller.
- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
detection first.
Example:
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
intcmux4@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
* Marvell Orion Interrupt controller
Required properties
- compatible : Should be "marvell,orion-intc".
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. Supported value is <1>.
- interrupt-controller : Declare this node to be an interrupt controller.
- reg : Interrupt mask address. A list of 4 byte ranges, one per controller.
One entry in the list represents 32 interrupts.
Example:
intc: interrupt-controller {
compatible = "marvell,orion-intc", "marvell,intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xfed20204 0x04>,
<0xfed20214 0x04>;
};
Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP/Orion Interrupt controller bindings
maintainers:
- Thomas Gleixner <tglx@linutronix.de>
- Jason Cooper <jason@lakedaemon.net>
- Marc Zyngier <maz@kernel.org>
- Rob Herring <robh+dt@kernel.org>
allOf:
- if:
properties:
compatible:
not:
contains:
const: marvell,orion-intc
then:
required:
- mrvl,intc-nr-irqs
- if:
properties:
compatible:
contains:
enum:
- mrvl,mmp-intc
- mrvl,mmp2-intc
then:
properties:
reg:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- marvell,mmp3-intc
- mrvl,mmp2-mux-intc
then:
properties:
reg:
minItems: 2
- if:
properties:
compatible:
contains:
const: mrvl,mmp2-mux-intc
then:
properties:
interrupts:
maxItems: 1
reg-names:
items:
- const: 'mux status'
- const: 'mux mask'
required:
- interrupts
else:
properties:
interrupts: false
properties:
'#interrupt-cells':
const: 1
compatible:
enum:
- mrvl,mmp-intc
- mrvl,mmp2-intc
- marvell,mmp3-intc
- marvell,orion-intc
- mrvl,mmp2-mux-intc
reg:
minItems: 1
maxItems: 2
reg-names: true
interrupts: true
interrupt-controller: true
mrvl,intc-nr-irqs:
description: |
Specifies the number of interrupts in the interrupt controller.
$ref: /schemas/types.yaml#/definitions/uint32
mrvl,clr-mfp-irq:
description: |
Specifies the interrupt that needs to clear MFP edge detection first.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- '#interrupt-cells'
- compatible
- reg
- interrupt-controller
additionalProperties: false
examples:
- |
interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
interrupt-controller@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
- |
interrupt-controller@fed20204 {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xfed20204 0x04>,
<0xfed20214 0x04>;
};
...
Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt deleted 100644 → 0
View file @ 1d8ce0e0
DT bindings for the Renesas RZ/A1 Interrupt Controller
The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
RZ/A1 and RZ/A2 SoCs:
- IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
interrupts,
- NMI edge select.
Required properties:
- compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
fallback.
Examples with soctypes are:
- "renesas,r7s72100-irqc" (RZ/A1H)
- "renesas,r7s9210-irqc" (RZ/A2M)
- #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
in interrupts.txt in this directory)
- #address-cells: Must be zero
- interrupt-controller: Marks the device as an interrupt controller
- reg: Base address and length of the memory resource used by the interrupt
controller
- interrupt-map: Specifies the mapping from external interrupts to GIC
interrupts
- interrupt-map-mask: Must be <7 0>
Example:
irqc: interrupt-controller@fcfef800 {
compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0xfcfef800 0x6>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <7 0>;
};
Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.yaml 0 → 100644
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/A1 Interrupt Controller
maintainers:
- Chris Brandt <chris.brandt@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
RZ/A2 SoCs:
- IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
- NMI edge select.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- enum:
- renesas,r7s72100-irqc # RZ/A1H
- renesas,r7s9210-irqc # RZ/A2M
- const: renesas,rza1-irqc
'#interrupt-cells':
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
interrupt-map:
maxItems: 8
description: Specifies the mapping from external interrupts to GIC interrupts.
interrupt-map-mask:
items:
- const: 7
- const: 0
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
- interrupt-map
- interrupt-map-mask
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
irqc: interrupt-controller@fcfef800 {
compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0xfcfef800 0x6>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <7 0>;
};
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
View file @ 44197797
......@@ -32,6 +32,7 @@ properties:
- enum:
- renesas,ipmmu-r8a774a1 # RZ/G2M
- renesas,ipmmu-r8a774b1 # RZ/G2N
- renesas,ipmmu-r8a774e1 # RZ/G2H
- renesas,ipmmu-r8a774c0 # RZ/G2E
- renesas,ipmmu-r8a7795 # R-Car H3
- renesas,ipmmu-r8a7796 # R-Car M3-W
......
Documentation/devicetree/bindings/leds/backlight/gpio-backlight.txt deleted 100644 → 0
View file @ 1d8ce0e0
gpio-backlight bindings
Required properties:
- compatible: "gpio-backlight"
- gpios: describes the gpio that is used for enabling/disabling the backlight.
refer to bindings/gpio/gpio.txt for more details.
Optional properties:
- default-on: enable the backlight at boot.
Example:
backlight {
compatible = "gpio-backlight";
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
default-on;
};
Documentation/devicetree/bindings/leds/backlight/gpio-backlight.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/backlight/gpio-backlight.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: gpio-backlight bindings
maintainers:
- Lee Jones <lee.jones@linaro.org>
- Daniel Thompson <daniel.thompson@linaro.org>
- Jingoo Han <jingoohan1@gmail.com>
properties:
compatible:
const: gpio-backlight
gpios:
description: The gpio that is used for enabling/disabling the backlight.
maxItems: 1
default-on:
description: enable the backlight at boot.
type: boolean
required:
- compatible
- gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
backlight {
compatible = "gpio-backlight";
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
default-on;
};
...
Documentation/devicetree/bindings/leds/backlight/led-backlight.txt deleted 100644 → 0
View file @ 1d8ce0e0
led-backlight bindings
This binding is used to describe a basic backlight device made of LEDs.
It can also be used to describe a backlight device controlled by the output of
a LED driver.
Required properties:
- compatible: "led-backlight"
- leds: a list of LEDs
Optional properties:
- brightness-levels: Array of distinct brightness levels. The levels must be
in the range accepted by the underlying LED devices.
This is used to translate a backlight brightness level
into a LED brightness level. If it is not provided, the
identity mapping is used.
- default-brightness-level: The default brightness level.
Example:
backlight {
compatible = "led-backlight";
leds = <&led1>, <&led2>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml 0 → 100644
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/backlight/led-backlight.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: led-backlight bindings
maintainers:
- Lee Jones <lee.jones@linaro.org>
- Daniel Thompson <daniel.thompson@linaro.org>
- Jingoo Han <jingoohan1@gmail.com>
description:
This binding is used to describe a basic backlight device made of LEDs. It
can also be used to describe a backlight device controlled by the output of
a LED driver.
properties:
compatible:
const: led-backlight
leds:
description: A list of LED nodes
$ref: /schemas/types.yaml#/definitions/phandle-array
brightness-levels:
description:
Array of distinct brightness levels. The levels must be in the range
accepted by the underlying LED devices. This is used to translate a
backlight brightness level into a LED brightness level. If it is not
provided, the identity mapping is used.
$ref: /schemas/types.yaml#/definitions/uint32-array
default-brightness-level:
description:
The default brightness level (index into the array defined by the
"brightness-levels" property).
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- leds
additionalProperties: false
examples:
- |
backlight {
compatible = "led-backlight";
leds = <&led1>, <&led2>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
...
Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt deleted 100644 → 0
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pwm-backlight bindings
Required properties:
- compatible: "pwm-backlight"
- pwms: OF device-tree PWM specification (see PWM binding[0])
- power-supply: regulator for supply voltage
Optional properties:
- pwm-names: a list of names for the PWM devices specified in the
"pwms" property (see PWM binding[0])
- enable-gpios: contains a single GPIO specifier for the GPIO which enables
and disables the backlight (see GPIO binding[1])
- post-pwm-on-delay-ms: Delay in ms between setting an initial (non-zero) PWM
and enabling the backlight using GPIO.
- pwm-off-delay-ms: Delay in ms between disabling the backlight using GPIO
and setting PWM value to 0.
- brightness-levels: Array of distinct brightness levels. Typically these
are in the range from 0 to 255, but any range starting at
0 will do. The actual brightness level (PWM duty cycle)
will be interpolated from these values. 0 means a 0% duty
cycle (darkest/off), while the last value in the array
represents a 100% duty cycle (brightest).
- default-brightness-level: The default brightness level (index into the
array defined by the "brightness-levels" property).
- num-interpolated-steps: Number of interpolated steps between each value
of brightness-levels table. This way a high
resolution pwm duty cycle can be used without
having to list out every possible value in the
brightness-level array.
[0]: Documentation/devicetree/bindings/pwm/pwm.txt
[1]: Documentation/devicetree/bindings/gpio/gpio.txt
Example:
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
post-pwm-on-delay-ms = <10>;
pwm-off-delay-ms = <10>;
};
Example using num-interpolation-steps:
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 2048 4096 8192 16384 65535>;
num-interpolated-steps = <2048>;
default-brightness-level = <4096>;
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
};
Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml 0 → 100644
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: pwm-backlight bindings
maintainers:
- Lee Jones <lee.jones@linaro.org>
- Daniel Thompson <daniel.thompson@linaro.org>
- Jingoo Han <jingoohan1@gmail.com>
properties:
compatible:
const: pwm-backlight
pwms:
maxItems: 1
pwm-names: true
power-supply:
description: regulator for supply voltage
enable-gpios:
description:
Contains a single GPIO specifier for the GPIO which enables and disables
the backlight.
maxItems: 1
post-pwm-on-delay-ms:
description:
Delay in ms between setting an initial (non-zero) PWM and enabling the
backlight using GPIO.
pwm-off-delay-ms:
description:
Delay in ms between disabling the backlight using GPIO and setting PWM
value to 0.
brightness-levels:
description:
Array of distinct brightness levels. Typically these are in the range
from 0 to 255, but any range starting at 0 will do. The actual brightness
level (PWM duty cycle) will be interpolated from these values. 0 means a
0% duty cycle (darkest/off), while the last value in the array represents
a 100% duty cycle (brightest).
$ref: /schemas/types.yaml#/definitions/uint32-array
default-brightness-level:
description:
The default brightness level (index into the array defined by the
"brightness-levels" property).
$ref: /schemas/types.yaml#/definitions/uint32
num-interpolated-steps:
description:
Number of interpolated steps between each value of brightness-levels
table. This way a high resolution pwm duty cycle can be used without
having to list out every possible value in the brightness-level array.
$ref: /schemas/types.yaml#/definitions/uint32
dependencies:
default-brightness-level: [brightness-levels]
num-interpolated-steps: [brightness-levels]
required:
- compatible
- pwms
- power-supply
additionalProperties: false
examples:
- |
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
post-pwm-on-delay-ms = <10>;
pwm-off-delay-ms = <10>;
};
- |
// Example using num-interpolation-steps:
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 2048 4096 8192 16384 65535>;
num-interpolated-steps = <2048>;
default-brightness-level = <4096>;
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
};
...
Documentation/devicetree/bindings/media/i2c/adv7180.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Analog Devices ADV7180 analog video decoder family
The adv7180 family devices are used to capture analog video to different
digital interfaces like MIPI CSI-2 or parallel video.
Required Properties :
- compatible : value must be one of
"adi,adv7180"
"adi,adv7180cp"
"adi,adv7180st"
"adi,adv7182"
"adi,adv7280"
"adi,adv7280-m"
"adi,adv7281"
"adi,adv7281-m"
"adi,adv7281-ma"
"adi,adv7282"
"adi,adv7282-m"
Device nodes of "adi,adv7180cp" and "adi,adv7180st" must contain one
'port' child node per device input and output port, in accordance with the
video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The port
nodes are numbered as follows.
Port adv7180cp adv7180st
-------------------------------------------------------------------
Input 0-2 0-5
Output 3 6
The digital output port node must contain at least one endpoint.
Optional Properties :
- powerdown-gpios: reference to the GPIO connected to the powerdown pin,
if any.
Example:
i2c0@1c22000 {
...
...
adv7180@21 {
compatible = "adi,adv7180";
reg = <0x21>;
};
...
};
Documentation/devicetree/bindings/media/i2c/adv7180.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/adv7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADV7180 analog video decoder family
maintainers:
- Lars-Peter Clausen <lars@metafoo.de>
description:
The adv7180 family devices are used to capture analog video to different
digital interfaces like MIPI CSI-2 or parallel video.
properties:
compatible:
items:
- enum:
- adi,adv7180
- adi,adv7180cp
- adi,adv7180st
- adi,adv7182
- adi,adv7280
- adi,adv7280-m
- adi,adv7281
- adi,adv7281-m
- adi,adv7281-ma
- adi,adv7282
- adi,adv7282-m
reg:
maxItems: 1
powerdown-gpios:
maxItems: 1
port:
type: object
description:
A node containing a single endpoint as doucmented in
Documentation/devicetree/bindings/media/video-interfaces.txt
ports:
type: object
description:
A node containing input and output port nodes with endpoint definitions
as documented in
Documentation/devicetree/bindings/media/video-interfaces.txt
additionalProperties: false
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
items:
- enum:
- adi,adv7180
- adi,adv7182
- adi,adv7280
- adi,adv7280-m
- adi,adv7281
- adi,adv7281-m
- adi,adv7281-ma
- adi,adv7282
- adi,adv7282-m
then:
required:
- port
- if:
properties:
compatible:
contains:
const: adi,adv7180cp
then:
properties:
ports:
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
port@3:
type: object
description: Output port
patternProperties:
"^port@[0-2]$":
type: object
description: Input port
required:
- port@3
additionalProperties: false
required:
- ports
- if:
properties:
compatible:
contains:
const: adi,adv7180st
then:
properties:
ports:
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
port@6:
type: object
description: Output port
patternProperties:
"^port@[0-5]$":
type: object
description: Input port
required:
- port@6
additionalProperties: false
required:
- ports
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
};
};
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
adv7180_out: endpoint {
remote-endpoint = <&vin4_in>;
};
};
};
};
};
Documentation/devicetree/bindings/media/i2c/imx274.txt
View file @ 44197797
......@@ -13,6 +13,11 @@ Required Properties:
Optional Properties:
- reset-gpios: Sensor reset GPIO
- clocks: Reference to the input clock.
- clock-names: Should be "inck".
- VANA-supply: Sensor 2.8v analog supply.
- VDIG-supply: Sensor 1.8v digital core supply.
- VDDL-supply: Sensor digital IO 1.2v supply.
The imx274 device node should contain one 'port' child node with
an 'endpoint' subnode. For further reading on port node refer to
......
Documentation/devicetree/bindings/media/xilinx/video.txt
View file @ 44197797
......@@ -32,4 +32,4 @@ The following properties are common to all Xilinx video IP cores.
defaults to "mono".
[UG934] http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf
[UG934] https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf
Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt deleted 100644 → 0
View file @ 1d8ce0e0
Freescale Multi Mode DDR controller (MMDC)
Required properties :
- compatible : should be one of following:
for i.MX6Q/i.MX6DL:
- "fsl,imx6q-mmdc";
for i.MX6QP:
- "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
for i.MX6SL:
- "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
for i.MX6SLL:
- "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
for i.MX6SX:
- "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
for i.MX6UL/i.MX6ULL/i.MX6ULZ:
- "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
for i.MX7ULP:
- "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
- reg : address and size of MMDC DDR controller registers
Optional properties :
- clocks : the clock provided by the SoC to access the MMDC registers
Example :
mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
mmdc1: memory-controller@21b4000 { /* MMDC1 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
status = "disabled";
};
Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Multi Mode DDR controller (MMDC)
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
oneOf:
- const: fsl,imx6q-mmdc
- items:
- enum:
- fsl,imx6qp-mmdc
- fsl,imx6sl-mmdc
- fsl,imx6sll-mmdc
- fsl,imx6sx-mmdc
- fsl,imx6ul-mmdc
- fsl,imx7ulp-mmdc
- const: fsl,imx6q-mmdc
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
memory-controller@21b0000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
memory-controller@21b4000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
};
Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
View file @ 44197797
......@@ -37,7 +37,7 @@ syscon as a means to arbitrate access.
[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
[3] https://en.wikipedia.org/wiki/Super_I/O
Required properties
......
Documentation/devicetree/bindings/mfd/da9062.txt
View file @ 44197797
* Dialog DA9062 Power Management Integrated Circuit (PMIC)
Product information for the DA9062 and DA9061 devices can be found here:
- http://www.dialog-semiconductor.com/products/da9062
- http://www.dialog-semiconductor.com/products/da9061
- https://www.dialog-semiconductor.com/products/da9062
- https://www.dialog-semiconductor.com/products/da9061
The DA9062 PMIC consists of:
......
Documentation/devicetree/bindings/mfd/syscon.yaml
View file @ 44197797
......@@ -45,7 +45,8 @@ properties:
- contains:
const: syscon
additionalItems: true
minItems: 2
maxItems: 4 # Should be enough
reg:
maxItems: 1
......
Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.txt deleted 100644 → 0
View file @ 1d8ce0e0
OLPC XO-1.75 Embedded Controller
Required properties:
- compatible: Should be "olpc,xo1.75-ec".
- cmd-gpios: gpio specifier of the CMD pin
The embedded controller requires the SPI controller driver to signal readiness
to receive a transfer (that is, when TX FIFO contains the response data) by
strobing the ACK pin with the ready signal. See the "ready-gpios" property of the
SSP binding as documented in:
<Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
Example:
&ssp3 {
spi-slave;
ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/misc/olpc,xo1.75-ec.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OLPC XO-1.75 Embedded Controller bindings
description: |
This binding describes the Embedded Controller acting as a SPI bus master
on a OLPC XO-1.75 laptop computer.
The embedded controller requires the SPI controller driver to signal
readiness to receive a transfer (that is, when TX FIFO contains the
response data) by strobing the ACK pin with the ready signal. See the
"ready-gpios" property of the SSP binding as documented in:
<Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
compatible:
const: olpc,xo1.75-ec
cmd-gpios:
description: GPIO uspecifier of the CMD pin
maxItems: 1
required:
- compatible
- cmd-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
spi-slave;
ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};
...
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
The Enhanced Secure Digital Host Controller on Freescale i.MX family
provides an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
Required properties:
- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
"fsl,imx25-esdhc"
"fsl,imx35-esdhc"
"fsl,imx51-esdhc"
"fsl,imx53-esdhc"
"fsl,imx6q-usdhc"
"fsl,imx6sl-usdhc"
"fsl,imx6sx-usdhc"
"fsl,imx6ull-usdhc"
"fsl,imx7d-usdhc"
"fsl,imx7ulp-usdhc"
"fsl,imx8mq-usdhc"
"fsl,imx8mm-usdhc"
"fsl,imx8mn-usdhc"
"fsl,imx8mp-usdhc"
"fsl,imx8qm-usdhc"
"fsl,imx8qxp-usdhc"
Optional properties:
- fsl,wp-controller : Indicate to use controller internal write protection
- fsl,delay-line : Specify the number of delay cells for override mode.
This is used to set the clock delay for DLL(Delay Line) on override mode
to select a proper data sampling window in case the clock quality is not good
due to signal path is too long on the board. Please refer to eSDHC/uSDHC
chapter, DLL (Delay Line) section in RM for details.
- voltage-ranges : Specify the voltage range in case there are software
transparent level shifters on the outputs of the controller. Two cells are
required, first cell specifies minimum slot voltage (mV), second cell
specifies maximum slot voltage (mV). Several ranges could be specified.
- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
in tuning procedure.
- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
The uSDHC use one delay cell as default increasing step to do tuning process.
This property allows user to change the tuning step to more than one delay
cells which is useful for some special boards or cards when the default
tuning step can't find the proper delay window within limited tuning retries.
- fsl,strobe-dll-delay-target: Specify the strobe dll control slave delay target.
This delay target programming host controller loopback read clock, and this
property allows user to change the delay target for the strobe input read clock.
If not use this property, driver default set the delay target to value 7.
Only eMMC HS400 mode need to take care of this property.
Examples:
esdhc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
fsl,wp-controller;
};
esdhc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
};
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
allOf:
- $ref: "mmc-controller.yaml"
description: |
The Enhanced Secure Digital Host Controller on Freescale i.MX family
provides an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
properties:
compatible:
enum:
- fsl,imx25-esdhc
- fsl,imx35-esdhc
- fsl,imx51-esdhc
- fsl,imx53-esdhc
- fsl,imx6q-usdhc
- fsl,imx6sl-usdhc
- fsl,imx6sx-usdhc
- fsl,imx6ull-usdhc
- fsl,imx7d-usdhc
- fsl,imx7ulp-usdhc
- fsl,imx8mq-usdhc
- fsl,imx8mm-usdhc
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,wp-controller:
description: |
boolean, if present, indicate to use controller internal write protection.
type: boolean
fsl,delay-line:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the number of delay cells for override mode.
This is used to set the clock delay for DLL(Delay Line) on override mode
to select a proper data sampling window in case the clock quality is not good
due to signal path is too long on the board. Please refer to eSDHC/uSDHC
chapter, DLL (Delay Line) section in RM for details.
default: 0
voltage-ranges:
$ref: '/schemas/types.yaml#/definitions/uint32-matrix'
description: |
Specify the voltage range in case there are software transparent level
shifters on the outputs of the controller. Two cells are required, first
cell specifies minimum slot voltage (mV), second cell specifies maximum
slot voltage (mV).
items:
items:
- description: value for minimum slot voltage
- description: value for maximum slot voltage
maxItems: 1
fsl,tuning-start-tap:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the start delay cell point when send first CMD19 in tuning procedure.
default: 0
fsl,tuning-step:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the increasing delay cell steps in tuning procedure.
The uSDHC use one delay cell as default increasing step to do tuning process.
This property allows user to change the tuning step to more than one delay
cells which is useful for some special boards or cards when the default
tuning step can't find the proper delay window within limited tuning retries.
default: 0
fsl,strobe-dll-delay-target:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the strobe dll control slave delay target.
This delay target programming host controller loopback read clock, and this
property allows user to change the delay target for the strobe input read clock.
If not use this property, driver default set the delay target to value 7.
Only eMMC HS400 mode need to take care of this property.
default: 0
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
mmc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
fsl,wp-controller;
};
mmc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
};
Documentation/devicetree/bindings/mmc/fsl-imx-mmc.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale Secure Digital Host Controller for i.MX2/3 series
This file documents differences to the properties defined in mmc.txt.
Required properties:
- compatible : Should be "fsl,<chip>-mmc", chip can be imx21 or imx31
Optional properties:
- dmas: One DMA phandle with arguments as defined by the devicetree bindings
of the used DMA controller.
- dma-names: Has to be "rx-tx".
Example:
sdhci1: sdhci@10014000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <11>;
dmas = <&dma 7>;
dma-names = "rx-tx";
bus-width = <4>;
cd-gpios = <&gpio3 29>;
};
Documentation/devicetree/bindings/mmc/fsl-imx-mmc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/fsl-imx-mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Secure Digital Host Controller for i.MX2/3 series
maintainers:
- Markus Pargmann <mpa@pengutronix.de>
allOf:
- $ref: "mmc-controller.yaml"
properties:
compatible:
oneOf:
- const: fsl,imx21-mmc
- const: fsl,imx31-mmc
- items:
- const: fsl,imx27-mmc
- const: fsl,imx21-mmc
reg:
maxItems: 1
interrupts:
maxItems: 1
dmas:
maxItems: 1
dma-names:
const: rx-tx
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
mmc@10014000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <11>;
dmas = <&dma 7>;
dma-names = "rx-tx";
bus-width = <4>;
cd-gpios = <&gpio3 29>;
};
Documentation/devicetree/bindings/mmc/mxs-mmc.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale MXS MMC controller
The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
to support MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties in mmc.txt
and the properties used by the mxsmmc driver.
Required properties:
- compatible: Should be "fsl,<chip>-mmc". The supported chips include
imx23 and imx28.
- interrupts: Should contain ERROR interrupt number
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and SSP DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Examples:
ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc";
reg = <0x80010000 2000>;
interrupts = <96>;
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
bus-width = <8>;
};
Documentation/devicetree/bindings/mmc/mxs-mmc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mxs-mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MXS MMC controller
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
to support MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties in mmc.txt
and the properties used by the mxsmmc driver.
allOf:
- $ref: "mmc-controller.yaml"
properties:
compatible:
enum:
- fsl,imx23-mmc
- fsl,imx28-mmc
reg:
maxItems: 1
interrupts:
maxItems: 1
dmas:
maxItems: 1
dma-names:
const: rx-tx
required:
- compatible
- reg
- interrupts
- dmas
- dma-names
unevaluatedProperties: false
examples:
- |
mmc@80010000 {
compatible = "fsl,imx28-mmc";
reg = <0x80010000 2000>;
interrupts = <96>;
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
bus-width = <8>;
};
Documentation/devicetree/bindings/mtd/gpmi-nand.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale General-Purpose Media Interface (GPMI)
The GPMI nand controller provides an interface to control the
NAND flash chips.
Required properties:
- compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
* imx23
* imx28
* imx6q
* imx6sx
* imx7d
- reg : should contain registers location and length for gpmi and bch.
- reg-names: Should contain the reg names "gpmi-nand" and "bch"
- interrupts : BCH interrupt number.
- interrupt-names : Should be "bch".
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and GPMI DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
- clocks : clocks phandle and clock specifier corresponding to each clock
specified in clock-names.
- clock-names : The "gpmi_io" clock is always required. Which clocks are
exactly required depends on chip:
* imx23/imx28 : "gpmi_io"
* imx6q/sx : "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch"
* imx7d : "gpmi_io", "gpmi_bch_apb"
Optional properties:
- nand-on-flash-bbt: boolean to enable on flash bbt option if not
present false
- fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
strength required. The required ECC strength is
automatically discoverable for some flash
(e.g., according to the ONFI standard).
However, note that if this strength is not
discoverable or this property is not enabled,
the software may chooses an implementation-defined
ECC scheme.
- fsl,no-blockmark-swap: Don't swap the bad block marker from the OOB
area with the byte in the data area but rely on the
flash based BBT for identifying bad blocks.
NOTE: this is only valid in conjunction with
'nand-on-flash-bbt'.
WARNING: on i.MX28 blockmark swapping cannot be
disabled for the BootROM in the FCB. Thus,
partitions written from Linux with this feature
turned on may not be accessible by the BootROM
code.
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step. Needs to be a multiple of 2.
- nand-ecc-step-size: integer representing the number of data bytes
that are covered by a single ECC step. The driver
supports 512 and 1024.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
Examples:
gpmi-nand@8000c000 {
compatible = "fsl,imx28-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8000c000 2000>, <0x8000a000 2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <41>;
interrupt-names = "bch";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
partition@0 {
...
};
};
Documentation/devicetree/bindings/mtd/gpmi-nand.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale General-Purpose Media Interface (GPMI) binding
maintainers:
- Han Xu <han.xu@nxp.com>
allOf:
- $ref: "nand-controller.yaml"
description: |
The GPMI nand controller provides an interface to control the NAND
flash chips. The device tree may optionally contain sub-nodes
describing partitions of the address space. See partition.txt for
more detail.
properties:
compatible:
enum:
- fsl,imx23-gpmi-nand
- fsl,imx28-gpmi-nand
- fsl,imx6q-gpmi-nand
- fsl,imx6sx-gpmi-nand
- fsl,imx7d-gpmi-nand
reg:
items:
- description: Address and length of gpmi block.
- description: Address and length of bch block.
reg-names:
items:
- const: gpmi-nand
- const: bch
interrupts:
maxItems: 1
interrupt-names:
const: bch
dmas:
maxItems: 1
dma-names:
const: rx-tx
clocks:
minItems: 1
maxItems: 5
items:
- description: SoC gpmi io clock
- description: SoC gpmi apb clock
- description: SoC gpmi bch clock
- description: SoC gpmi bch apb clock
- description: SoC per1 bch clock
clock-names:
minItems: 1
maxItems: 5
items:
- const: gpmi_io
- const: gpmi_apb
- const: gpmi_bch
- const: gpmi_bch_apb
- const: per1_bch
fsl,use-minimum-ecc:
type: boolean
description: |
Protect this NAND flash with the minimum ECC strength required.
The required ECC strength is automatically discoverable for some
flash (e.g., according to the ONFI standard). However, note that
if this strength is not discoverable or this property is not enabled,
the software may chooses an implementation-defined ECC scheme.
fsl,no-blockmark-swap:
type: boolean
description: |
Don't swap the bad block marker from the OOB area with the byte in
the data area but rely on the flash based BBT for identifying bad blocks.
NOTE: this is only valid in conjunction with 'nand-on-flash-bbt'.
WARNING: on i.MX28 blockmark swapping cannot be disabled for the BootROM
in the FCB. Thus, partitions written from Linux with this feature turned
on may not be accessible by the BootROM code.
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
- dmas
- dma-names
unevaluatedProperties: false
examples:
- |
nand-controller@8000c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-gpmi-nand";
reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <41>;
interrupt-names = "bch";
clocks = <&clks 50>;
clock-names = "gpmi_io";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
};
Documentation/devicetree/bindings/mtd/mxc-nand.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Freescale's mxc_nand
Required properties:
- compatible: "fsl,imxXX-nand"
- reg: address range of the nfc block
- interrupts: irq to be used
- nand-bus-width: see nand-controller.yaml
- nand-ecc-mode: see nand-controller.yaml
- nand-on-flash-bbt: see nand-controller.yaml
Example:
nand@d8000000 {
compatible = "fsl,imx27-nand";
reg = <0xd8000000 0x1000>;
interrupts = <29>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
};
Documentation/devicetree/bindings/mtd/mxc-nand.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mxc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale's mxc_nand binding
maintainers:
- Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
allOf:
- $ref: "nand-controller.yaml"
properties:
compatible:
const: fsl,imx27-nand
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
nand-controller@d8000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx27-nand";
reg = <0xd8000000 0x1000>;
interrupts = <29>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
};
Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: CPSW Port's Interface Mode Selection PHY Tree Bindings
maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
description: |
TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
The interface mode is selected by configuring the MII mode selection register(s)
(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
bit fields placement in SCM are different between SoCs while fields meaning
is the same.
+--------------+
+-------------------------------+ |SCM |
| CPSW | | +---------+ |
| +--------------------------------+gmii_sel | |
| | | | +---------+ |
| +----v---+ +--------+ | +--------------+
| |Port 1..<--+-->GMII/MII<------->
| | | | | | |
| +--------+ | +--------+ |
| | |
| | +--------+ |
| | | RMII <------->
| +--> | |
| | +--------+ |
| | |
| | +--------+ |
| | | RGMII <------->
| +--> | |
| +--------+ |
+-------------------------------+
CPSW Port's Interface Mode Selection PHY describes MII interface mode between
CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
|
CPSW Port's Interface Mode Selection PHY device should defined as child device
of SCM node (scm_conf) and can be attached to each CPSW port node using standard
PHY bindings.
properties:
compatible:
enum:
- ti,am3352-phy-gmii-sel
- ti,dra7xx-phy-gmii-sel
- ti,am43xx-phy-gmii-sel
- ti,dm814-phy-gmii-sel
- ti,am654-phy-gmii-sel
reg:
description: Address and length of the register set for the device
'#phy-cells': true
allOf:
- if:
properties:
compatible:
contains:
enum:
- ti,dra7xx-phy-gmii-sel
- ti,dm814-phy-gmii-sel
- ti,am654-phy-gmii-sel
then:
properties:
'#phy-cells':
const: 1
description: CPSW port number (starting from 1)
- if:
properties:
compatible:
contains:
enum:
- ti,am3352-phy-gmii-sel
- ti,am43xx-phy-gmii-sel
then:
properties:
'#phy-cells':
const: 2
description: |
- CPSW port number (starting from 1)
- RMII refclk mode
required:
- compatible
- reg
- '#phy-cells'
additionalProperties: false
examples:
- |
phy_gmii_sel: phy-gmii-sel@650 {
compatible = "ti,am3352-phy-gmii-sel";
reg = <0x650 0x4>;
#phy-cells = <2>;
};
Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt deleted 100644 → 0
View file @ 1d8ce0e0
CPSW Port's Interface Mode Selection PHY Tree Bindings
-----------------------------------------------
TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
The interface mode is selected by configuring the MII mode selection register(s)
(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
bit fields placement in SCM are different between SoCs while fields meaning
is the same.
+--------------+
+-------------------------------+ |SCM |
| CPSW | | +---------+ |
| +--------------------------------+gmii_sel | |
| | | | +---------+ |
| +----v---+ +--------+ | +--------------+
| |Port 1..<--+-->GMII/MII<------->
| | | | | | |
| +--------+ | +--------+ |
| | |
| | +--------+ |
| | | RMII <------->
| +--> | |
| | +--------+ |
| | |
| | +--------+ |
| | | RGMII <------->
| +--> | |
| +--------+ |
+-------------------------------+
CPSW Port's Interface Mode Selection PHY describes MII interface mode between
CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
CPSW Port's Interface Mode Selection PHY device should defined as child device
of SCM node (scm_conf) and can be attached to each CPSW port node using standard
PHY bindings (See phy/phy-bindings.txt).
Required properties:
- compatible : Should be "ti,am3352-phy-gmii-sel" for am335x platform
"ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
"ti,am43xx-phy-gmii-sel" for am43xx platform
"ti,dm814-phy-gmii-sel" for dm814x platform
"ti,am654-phy-gmii-sel" for AM654x/J721E platform
- reg : Address and length of the register set for the device
- #phy-cells : must be 2.
cell 1 - CPSW port number (starting from 1)
cell 2 - RMII refclk mode
Examples:
phy_gmii_sel: phy-gmii-sel {
compatible = "ti,am3352-phy-gmii-sel";
reg = <0x650 0x4>;
#phy-cells = <2>;
};
mac: ethernet@4a100000 {
compatible = "ti,am335x-cpsw","ti,cpsw";
...
cpsw_emac0: slave@4a100200 {
...
phys = <&phy_gmii_sel 1 1>;
};
cpsw_emac1: slave@4a100300 {
...
phys = <&phy_gmii_sel 2 1>;
};
};
Documentation/devicetree/bindings/property-units.txt
View file @ 44197797
......@@ -17,6 +17,7 @@ Time/Frequency
-ms : millisecond
-us : microsecond
-ns : nanosecond
-ps : picosecond
Distance
----------------------------------------
......
Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
View file @ 44197797
......@@ -18,9 +18,6 @@ description: |+
Be aware that the clocksource driver supports only uniprocessor systems.
allOf:
- $ref: pwm.yaml#
properties:
compatible:
enum:
......@@ -63,7 +60,8 @@ properties:
interrupts:
description:
One interrupt per timer, starting at timer 0.
One interrupt per timer, starting at timer 0. Necessary only for SoCs which
use PWM clocksource.
minItems: 1
maxItems: 5
......@@ -88,12 +86,27 @@ required:
- clocks
- clock-names
- compatible
- interrupts
- "#pwm-cells"
- reg
additionalProperties: false
allOf:
- $ref: pwm.yaml#
- if:
properties:
compatible:
contains:
enum:
- samsung,s3c2410-pwm
- samsung,s3c6400-pwm
- samsung,s5p6440-pwm
- samsung,s5pc100-pwm
then:
required:
- interrupts
examples:
- |
pwm@7f006000 {
......
Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier reset controller
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
oneOf:
- description: System reset
enum:
- socionext,uniphier-ld4-reset
- socionext,uniphier-pro4-reset
- socionext,uniphier-sld8-reset
- socionext,uniphier-pro5-reset
- socionext,uniphier-pxs2-reset
- socionext,uniphier-ld6b-reset
- socionext,uniphier-ld11-reset
- socionext,uniphier-ld20-reset
- socionext,uniphier-pxs3-reset
- description: Media I/O (MIO) reset, SD reset
enum:
- socionext,uniphier-ld4-mio-reset
- socionext,uniphier-pro4-mio-reset
- socionext,uniphier-sld8-mio-reset
- socionext,uniphier-pro5-sd-reset
- socionext,uniphier-pxs2-sd-reset
- socionext,uniphier-ld11-mio-reset
- socionext,uniphier-ld11-sd-reset
- socionext,uniphier-ld20-sd-reset
- socionext,uniphier-pxs3-sd-reset
- description: Peripheral reset
enum:
- socionext,uniphier-ld4-peri-reset
- socionext,uniphier-pro4-peri-reset
- socionext,uniphier-sld8-peri-reset
- socionext,uniphier-pro5-peri-reset
- socionext,uniphier-pxs2-peri-reset
- socionext,uniphier-ld11-peri-reset
- socionext,uniphier-ld20-peri-reset
- socionext,uniphier-pxs3-peri-reset
- description: Analog signal amplifier reset
enum:
- socionext,uniphier-ld11-adamv-reset
- socionext,uniphier-ld20-adamv-reset
"#reset-cells":
const: 1
additionalProperties: false
required:
- compatible
- "#reset-cells"
examples:
- |
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reset {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
// other nodes ...
};
- |
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reset {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
};
// other nodes ...
};
- |
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
reg = <0x59820000 0x200>;
reset {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
// other nodes ...
};
- |
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
reset {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
// other nodes ...
};
Documentation/devicetree/bindings/reset/uniphier-reset.txt
View file @ 44197797
UniPhier reset controller
System reset
------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-reset" - for LD4 SoC
"socionext,uniphier-pro4-reset" - for Pro4 SoC
"socionext,uniphier-sld8-reset" - for sLD8 SoC
"socionext,uniphier-pro5-reset" - for Pro5 SoC
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
"socionext,uniphier-ld11-reset" - for LD11 SoC
"socionext,uniphier-ld20-reset" - for LD20 SoC
"socionext,uniphier-pxs3-reset" - for PXs3 SoC
- #reset-cells: should be 1.
Example:
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reset {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
other nodes ...
};
Media I/O (MIO) reset, SD reset
-------------------------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-mio-reset" - for LD4 SoC
"socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
"socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
"socionext,uniphier-pro5-sd-reset" - for Pro5 SoC
"socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
"socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC
"socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
- #reset-cells: should be 1.
Example:
mioctrl@59810000 {
compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reset {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
};
other nodes ...
};
Peripheral reset
----------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-peri-reset" - for LD4 SoC
"socionext,uniphier-pro4-peri-reset" - for Pro4 SoC
"socionext,uniphier-sld8-peri-reset" - for sLD8 SoC
"socionext,uniphier-pro5-peri-reset" - for Pro5 SoC
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC
"socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
- #reset-cells: should be 1.
Example:
perictrl@59820000 {
compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
reset {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
other nodes ...
};
Analog signal amplifier reset
-----------------------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
"socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
- #reset-cells: should be 1.
Example:
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
adamv_rst: reset {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
other nodes ...
};
UniPhier glue reset controller
Peripheral core reset in glue layer
......
Documentation/devicetree/bindings/rtc/imxdi-rtc.txt deleted 100644 → 0
View file @ 1d8ce0e0
* i.MX25 Real Time Clock controller
Required properties:
- compatible: should be: "fsl,imx25-rtc"
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: should contain the phandle for the rtc clock
- interrupts: rtc alarm interrupt
Optional properties:
- interrupts: dryice security violation interrupt (second entry)
Example:
rtc@53ffc000 {
compatible = "fsl,imx25-rtc";
reg = <0x53ffc000 0x4000>;
clocks = <&clks 81>;
interrupts = <25 56>;
};
Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/imxdi-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX25 Real Time Clock controller
maintainers:
- Roland Stigge <stigge@antcom.de>
properties:
compatible:
const: fsl,imx25-rtc
reg:
maxItems: 1
interrupts:
items:
- description: rtc alarm interrupt
- description: dryice security violation interrupt
minItems: 1
maxItems: 2
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
rtc@53ffc000 {
compatible = "fsl,imx25-rtc";
reg = <0x53ffc000 0x4000>;
clocks = <&clks 81>;
interrupts = <25>, <56>;
};
Documentation/devicetree/bindings/rtc/sa1100-rtc.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Marvell Real Time Clock controller
Required properties:
- compatible: should be "mrvl,sa1100-rtc"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: Should be two. The first interrupt number is the rtc alarm
interrupt and the second interrupt number is the rtc hz interrupt.
- interrupt-names: Assign name of irq resource.
Example:
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <5>, <6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
};
Documentation/devicetree/bindings/rtc/sa1100-rtc.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/sa1100-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Real Time Clock controller bindings
allOf:
- $ref: rtc.yaml#
maintainers:
- Alessandro Zummo <a.zummo@towertech.it>
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Rob Herring <robh+dt@kernel.org>
properties:
compatible:
enum:
- mrvl,sa1100-rtc
- mrvl,mmp-rtc
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
minItems: 2
interrupt-names:
items:
- const: 'rtc 1Hz'
- const: 'rtc alarm'
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <5>, <6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
};
...
Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
View file @ 44197797
......@@ -5,7 +5,8 @@ SPI0, and the other known as the "Universal SPI Master"; part of the
auxiliary block. This binding applies to the SPI0 controller.
Required properties:
- compatible: Should be "brcm,bcm2835-spi".
- compatible: Should be one of "brcm,bcm2835-spi" for BCM2835/2836/2837 or
"brcm,bcm2711-spi" for BCM2711 or "brcm,bcm7211-spi" for BCM7211.
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: The clock feeding the SPI controller.
......
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View file @ 44197797
......@@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: QCOM SoC Temperature Sensor (TSENS)
maintainers:
- Amit Kucheria <amit.kucheria@linaro.org>
- Amit Kucheria <amitk@kernel.org>
description: |
QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
......
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
Required properties:
- compatible : Must include "fsl,qoriq-tmu" or "fsl,imx8mq-tmu". The
version of the device is determined by the TMU IP Block Revision
Register (IPBRR0) at offset 0x0BF8.
Table of correspondences between IPBRR0 values and example chips:
Value Device
---------- -----
0x01900102 T1040
- reg : Address range of TMU registers.
- interrupts : Contains the interrupt for TMU.
- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
the SoC reference manual. The first cell is TTR0CR, the second is
TTR1CR, etc.
- fsl,tmu-calibration : A list of cell pairs containing temperature
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
site ID, and represents the "n" in TRITSRn and TRATSRn.
Optional property:
- little-endian : If present, the TMU registers are little endian. If absent,
the default is big endian.
- clocks : the clock for clocking the TMU silicon.
Example:
tmu@f0000 {
compatible = "fsl,qoriq-tmu";
reg = <0xf0000 0x1000>;
interrupts = <18 2 0 0>;
fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
fsl,tmu-calibration = <0x00000000 0x00000025
0x00000001 0x00000028
0x00000002 0x0000002d
0x00000003 0x00000031
0x00000004 0x00000036
0x00000005 0x0000003a
0x00000006 0x00000040
0x00000007 0x00000044
0x00000008 0x0000004a
0x00000009 0x0000004f
0x0000000a 0x00000054
0x00010000 0x0000000d
0x00010001 0x00000013
0x00010002 0x00000019
0x00010003 0x0000001f
0x00010004 0x00000025
0x00010005 0x0000002d
0x00010006 0x00000033
0x00010007 0x00000043
0x00010008 0x0000004b
0x00010009 0x00000053
0x00020000 0x00000010
0x00020001 0x00000017
0x00020002 0x0000001f
0x00020003 0x00000029
0x00020004 0x00000031
0x00020005 0x0000003c
0x00020006 0x00000042
0x00020007 0x0000004d
0x00020008 0x00000056
0x00030000 0x00000012
0x00030001 0x0000001d>;
#thermal-sensor-cells = <1>;
};
Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qoriq-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
description: |
The version of the device is determined by the TMU IP Block Revision
Register (IPBRR0) at offset 0x0BF8.
Table of correspondences between IPBRR0 values and example chips:
Value Device
---------- -----
0x01900102 T1040
enum:
- fsl,qoriq-tmu
- fsl,imx8mq-tmu
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,tmu-range:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
description: |
The values to be programmed into TTRnCR, as specified by the SoC
reference manual. The first cell is TTR0CR, the second is TTR1CR, etc.
maxItems: 4
fsl,tmu-calibration:
$ref: '/schemas/types.yaml#/definitions/uint32-matrix'
description: |
A list of cell pairs containing temperature calibration data, as
specified by the SoC reference manual. The first cell of each pair
is the value to be written to TTCFGR, and the second is the value
to be written to TSCFGR.
items:
items:
- description: value for TTCFGR
- description: value for TSCFGR
minItems: 1
maxItems: 64
little-endian:
description: |
boolean, if present, the TMU registers are little endian. If absent,
the default is big endian.
type: boolean
clocks:
maxItems: 1
"#thermal-sensor-cells":
const: 1
required:
- compatible
- reg
- interrupts
- fsl,tmu-range
- fsl,tmu-calibration
- '#thermal-sensor-cells'
additionalProperties: false
examples:
- |
tmu@f0000 {
compatible = "fsl,qoriq-tmu";
reg = <0xf0000 0x1000>;
interrupts = <18 2 0 0>;
fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
fsl,tmu-calibration = <0x00000000 0x00000025>,
<0x00000001 0x00000028>,
<0x00000002 0x0000002d>,
<0x00000003 0x00000031>,
<0x00000004 0x00000036>,
<0x00000005 0x0000003a>,
<0x00000006 0x00000040>,
<0x00000007 0x00000044>,
<0x00000008 0x0000004a>,
<0x00000009 0x0000004f>,
<0x0000000a 0x00000054>,
<0x00010000 0x0000000d>,
<0x00010001 0x00000013>,
<0x00010002 0x00000019>,
<0x00010003 0x0000001f>,
<0x00010004 0x00000025>,
<0x00010005 0x0000002d>,
<0x00010006 0x00000033>,
<0x00010007 0x00000043>,
<0x00010008 0x0000004b>,
<0x00010009 0x00000053>,
<0x00020000 0x00000010>,
<0x00020001 0x00000017>,
<0x00020002 0x0000001f>,
<0x00020003 0x00000029>,
<0x00020004 0x00000031>,
<0x00020005 0x0000003c>,
<0x00020006 0x00000042>,
<0x00020007 0x0000004d>,
<0x00020008 0x00000056>,
<0x00030000 0x00000012>,
<0x00030001 0x0000001d>;
#thermal-sensor-cells = <1>;
};
Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt deleted 100644 → 0
View file @ 1d8ce0e0
* Marvell MMP Timer controller
Required properties:
- compatible : Should be "mrvl,mmp-timer".
- reg : Address and length of the register set of timer controller.
- interrupts : Should be the interrupt number.
Optional properties:
- clocks : Should contain a single entry describing the clock input.
Example:
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
clocks = <&coreclk 2>;
};
Documentation/devicetree/bindings/timer/mrvl,mmp-timer.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/mrvl,mmp-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP Timer bindings
maintainers:
- Daniel Lezcano <daniel.lezcano@linaro.org>
- Thomas Gleixner <tglx@linutronix.de>
- Rob Herring <robh+dt@kernel.org>
properties:
$nodename:
pattern: '^timer@[a-f0-9]+$'
compatible:
const: mrvl,mmp-timer
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
clocks = <&coreclk 2>;
};
...
Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml 0 → 100644
View file @ 44197797
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/renesas,usb-xhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas USB xHCI controllers
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
allOf:
- $ref: "usb-hcd.yaml"
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,xhci-r8a7742 # RZ/G1H
- renesas,xhci-r8a7743 # RZ/G1M
- renesas,xhci-r8a7744 # RZ/G1N
- renesas,xhci-r8a7790 # R-Car H2
- renesas,xhci-r8a7791 # R-Car M2-W
- renesas,xhci-r8a7793 # R-Car M2-N
- const: renesas,rcar-gen2-xhci # R-Car Gen2 and RZ/G1
- items:
- enum:
- renesas,xhci-r8a774a1 # RZ/G2M
- renesas,xhci-r8a774b1 # RZ/G2N
- renesas,xhci-r8a774c0 # RZ/G2E
- renesas,xhci-r8a7795 # R-Car H3
- renesas,xhci-r8a7796 # R-Car M3-W
- renesas,xhci-r8a77961 # R-Car M3-W+
- renesas,xhci-r8a77965 # R-Car M3-N
- renesas,xhci-r8a77990 # R-Car E3
- const: renesas,rcar-gen3-xhci # R-Car Gen3 and RZ/G2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
phys:
maxItems: 1
phy-names:
maxItems: 1
items:
- const: usb
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- power-domains
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
reg = <0xee000000 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
};
Documentation/devicetree/bindings/usb/usb-xhci.txt
View file @ 44197797
......@@ -7,24 +7,6 @@ Required properties:
- "marvell,armada3700-xhci" for Armada 37xx SoCs
- "marvell,armada-375-xhci" for Armada 375 SoCs
- "marvell,armada-380-xhci" for Armada 38x SoCs
- "renesas,xhci-r8a7742" for r8a7742 SoC
- "renesas,xhci-r8a7743" for r8a7743 SoC
- "renesas,xhci-r8a7744" for r8a7744 SoC
- "renesas,xhci-r8a774a1" for r8a774a1 SoC
- "renesas,xhci-r8a774b1" for r8a774b1 SoC
- "renesas,xhci-r8a774c0" for r8a774c0 SoC
- "renesas,xhci-r8a7790" for r8a7790 SoC
- "renesas,xhci-r8a7791" for r8a7791 SoC
- "renesas,xhci-r8a7793" for r8a7793 SoC
- "renesas,xhci-r8a7795" for r8a7795 SoC
- "renesas,xhci-r8a7796" for r8a77960 SoC
- "renesas,xhci-r8a77961" for r8a77961 SoC
- "renesas,xhci-r8a77965" for r8a77965 SoC
- "renesas,xhci-r8a77990" for r8a77990 SoC
- "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 or RZ/G1 compatible
device
- "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 or RZ/G2 compatible
device
- "brcm,bcm7445-xhci" for Broadcom STB SoCs with XHCI
- "xhci-platform" (deprecated)
......
Documentation/devicetree/bindings/virtio/mmio.txt
View file @ 44197797
* virtio memory mapped device
See http://ozlabs.org/~rusty/virtio-spec/ for more details.
See https://ozlabs.org/~rusty/virtio-spec/ for more details.
Required properties:
......
MAINTAINERS
View file @ 44197797
......@@ -1082,6 +1082,7 @@ L: linux-media@vger.kernel.org
S: Supported
W: http://ez.analog.com/community/linux-device-drivers
F: drivers/media/i2c/adv7180.c
F: Documentation/devicetree/bindings/media/i2c/adv7180.yaml
ANALOG DEVICES INC ADV748X DRIVER
M: Kieran Bingham <kieran.bingham@ideasonboard.com>
......@@ -14309,7 +14310,7 @@ F: drivers/net/ethernet/qualcomm/rmnet/
F: include/linux/if_rmnet.h
QUALCOMM TSENS THERMAL DRIVER
M: Amit Kucheria <amit.kucheria@linaro.org>
M: Amit Kucheria <amitk@kernel.org>
L: linux-pm@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
......@@ -17011,7 +17012,7 @@ F: drivers/media/radio/radio-raremono.c
THERMAL
M: Zhang Rui <rui.zhang@intel.com>
M: Daniel Lezcano <daniel.lezcano@linaro.org>
R: Amit Kucheria <amit.kucheria@verdurent.com>
R: Amit Kucheria <amitk@kernel.org>
L: linux-pm@vger.kernel.org
S: Supported
Q: https://patchwork.kernel.org/project/linux-pm/list/
......
drivers/base/core.c
View file @ 44197797
......@@ -122,7 +122,7 @@ int device_links_read_lock_held(void)
* Check if @target depends on @dev or any device dependent on it (its child or
* its consumer etc). Return 1 if that is the case or 0 otherwise.
*/
static int device_is_dependent(struct device *dev, void *target)
int device_is_dependent(struct device *dev, void *target)
{
struct device_link *link;
int ret;
......
drivers/of/address.c
View file @ 44197797
......@@ -864,7 +864,7 @@ EXPORT_SYMBOL_GPL(of_address_to_resource);
/**
* of_iomap - Maps the memory mapped IO for a given device_node
* @device: the device whose io range will be mapped
* @np: the device whose io range will be mapped
* @index: index of the io range
*
* Returns a pointer to the mapped memory
......
drivers/of/of_reserved_mem.c
View file @ 44197797
......@@ -54,7 +54,7 @@ void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname,
struct reserved_mem *rmem = &reserved_mem[reserved_mem_count];
if (reserved_mem_count == ARRAY_SIZE(reserved_mem)) {
pr_err("not enough space all defined regions.\n");
pr_err("not enough space for all defined regions.\n");
return;
}
......@@ -69,7 +69,7 @@ void __init fdt_reserved_mem_save_node(unsigned long node, const char *uname,
/**
* __reserved_mem_alloc_size() - allocate reserved memory described by
* 'size', 'align' and 'alloc-ranges' properties.
* 'size', 'alignment' and 'alloc-ranges' properties.
*/
static int __init __reserved_mem_alloc_size(unsigned long node,
const char *uname, phys_addr_t *res_base, phys_addr_t *res_size)
......@@ -79,7 +79,7 @@ static int __init __reserved_mem_alloc_size(unsigned long node,
phys_addr_t base = 0, align = 0, size;
int len;
const __be32 *prop;
int nomap;
bool nomap;
int ret;
prop = of_get_flat_dt_prop(node, "size", &len);
......@@ -92,8 +92,6 @@ static int __init __reserved_mem_alloc_size(unsigned long node,
}
size = dt_mem_next_cell(dt_root_size_cells, &prop);
nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
prop = of_get_flat_dt_prop(node, "alignment", &len);
if (prop) {
if (len != dt_root_addr_cells * sizeof(__be32)) {
......@@ -104,11 +102,13 @@ static int __init __reserved_mem_alloc_size(unsigned long node,
align = dt_mem_next_cell(dt_root_addr_cells, &prop);
}
nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
/* Need adjust the alignment to satisfy the CMA requirement */
if (IS_ENABLED(CONFIG_CMA)
&& of_flat_dt_is_compatible(node, "shared-dma-pool")
&& of_get_flat_dt_prop(node, "reusable", NULL)
&& !of_get_flat_dt_prop(node, "no-map", NULL)) {
&& !nomap) {
unsigned long order =
max_t(unsigned long, MAX_ORDER - 1, pageblock_order);
......@@ -247,7 +247,7 @@ void __init fdt_init_reserved_mem(void)
int len;
const __be32 *prop;
int err = 0;
int nomap;
bool nomap;
nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
prop = of_get_flat_dt_prop(node, "phandle", &len);
......
drivers/of/property.c
View file @ 44197797
......@@ -1014,6 +1014,30 @@ static bool of_is_ancestor_of(struct device_node *test_ancestor,
return false;
}
/**
* of_get_next_parent_dev - Add device link to supplier from supplier phandle
* @np: device tree node
*
* Given a device tree node (@np), this function finds its closest ancestor
* device tree node that has a corresponding struct device.
*
* The caller of this function is expected to call put_device() on the returned
* device when they are done.
*/
static struct device *of_get_next_parent_dev(struct device_node *np)
{
struct device *dev = NULL;
of_node_get(np);
do {
np = of_get_next_parent(np);
if (np)
dev = get_dev_from_fwnode(&np->fwnode);
} while (np && !dev);
of_node_put(np);
return dev;
}
/**
* of_link_to_phandle - Add device link to supplier from supplier phandle
* @dev: consumer device
......@@ -1035,10 +1059,9 @@ static bool of_is_ancestor_of(struct device_node *test_ancestor,
static int of_link_to_phandle(struct device *dev, struct device_node *sup_np,
u32 dl_flags)
{
struct device *sup_dev;
struct device *sup_dev, *sup_par_dev;
int ret = 0;
struct device_node *tmp_np = sup_np;
int is_populated;
of_node_get(sup_np);
/*
......@@ -1075,16 +1098,43 @@ static int of_link_to_phandle(struct device *dev, struct device_node *sup_np,
return -EINVAL;
}
sup_dev = get_dev_from_fwnode(&sup_np->fwnode);
is_populated = of_node_check_flag(sup_np, OF_POPULATED);
of_node_put(sup_np);
if (!sup_dev && is_populated) {
if (!sup_dev && of_node_check_flag(sup_np, OF_POPULATED)) {
/* Early device without struct device. */
dev_dbg(dev, "Not linking to %pOFP - No struct device\n",
sup_np);
of_node_put(sup_np);
return -ENODEV;
} else if (!sup_dev) {
return -EAGAIN;
/*
* DL_FLAG_SYNC_STATE_ONLY doesn't block probing and supports
* cycles. So cycle detection isn't necessary and shouldn't be
* done.
*/
if (dl_flags & DL_FLAG_SYNC_STATE_ONLY) {
of_node_put(sup_np);
return -EAGAIN;
}
sup_par_dev = of_get_next_parent_dev(sup_np);
if (sup_par_dev && device_is_dependent(dev, sup_par_dev)) {
/* Cyclic dependency detected, don't try to link */
dev_dbg(dev, "Not linking to %pOFP - cycle detected\n",
sup_np);
ret = -EINVAL;
} else {
/*
* Can't check for cycles or no cycles. So let's try
* again later.
*/
ret = -EAGAIN;
}
of_node_put(sup_np);
put_device(sup_par_dev);
return ret;
}
of_node_put(sup_np);
if (!device_link_add(dev, sup_dev, dl_flags))
ret = -EINVAL;
put_device(sup_dev);
......@@ -1219,6 +1269,20 @@ DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-cells")
DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells")
DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells")
DEFINE_SIMPLE_PROP(extcon, "extcon", NULL)
DEFINE_SIMPLE_PROP(interrupts_extended, "interrupts-extended",
"#interrupt-cells")
DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", NULL)
DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells")
DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL)
DEFINE_SIMPLE_PROP(pinctrl0, "pinctrl-0", NULL)
DEFINE_SIMPLE_PROP(pinctrl1, "pinctrl-1", NULL)
DEFINE_SIMPLE_PROP(pinctrl2, "pinctrl-2", NULL)
DEFINE_SIMPLE_PROP(pinctrl3, "pinctrl-3", NULL)
DEFINE_SIMPLE_PROP(pinctrl4, "pinctrl-4", NULL)
DEFINE_SIMPLE_PROP(pinctrl5, "pinctrl-5", NULL)
DEFINE_SIMPLE_PROP(pinctrl6, "pinctrl-6", NULL)
DEFINE_SIMPLE_PROP(pinctrl7, "pinctrl-7", NULL)
DEFINE_SIMPLE_PROP(pinctrl8, "pinctrl-8", NULL)
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
DEFINE_SUFFIX_PROP(gpios, "-gpios", "#gpio-cells")
......@@ -1244,6 +1308,19 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_power_domains, },
{ .parse_prop = parse_hwlocks, },
{ .parse_prop = parse_extcon, },
{ .parse_prop = parse_interrupts_extended, },
{ .parse_prop = parse_nvmem_cells, },
{ .parse_prop = parse_phys, },
{ .parse_prop = parse_wakeup_parent, },
{ .parse_prop = parse_pinctrl0, },
{ .parse_prop = parse_pinctrl1, },
{ .parse_prop = parse_pinctrl2, },
{ .parse_prop = parse_pinctrl3, },
{ .parse_prop = parse_pinctrl4, },
{ .parse_prop = parse_pinctrl5, },
{ .parse_prop = parse_pinctrl6, },
{ .parse_prop = parse_pinctrl7, },
{ .parse_prop = parse_pinctrl8, },
{ .parse_prop = parse_regulators, },
{ .parse_prop = parse_gpio, },
{ .parse_prop = parse_gpios, },
......
drivers/of/unittest-data/tests-address.dtsi
View file @ 44197797
......@@ -23,13 +23,13 @@ device@70000000 {
};
bus@80000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000000 0x100000>;
dma-ranges = <0x10000000 0x0 0x40000000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
device@1000 {
reg = <0x1000 0x1000>;
reg = <0x0 0x1000 0x0 0x1000>;
};
};
......
drivers/of/unittest.c
View file @ 44197797
......@@ -900,7 +900,7 @@ static void __init of_unittest_parse_dma_ranges(void)
of_unittest_dma_ranges_one("/testcase-data/address-tests/device@70000000",
0x0, 0x20000000, 0x40000000);
of_unittest_dma_ranges_one("/testcase-data/address-tests/bus@80000000/device@1000",
0x10000000, 0x20000000, 0x40000000);
0x100000000, 0x20000000, 0x2000000000);
of_unittest_dma_ranges_one("/testcase-data/address-tests/pci@90000000",
0x80000000, 0x20000000, 0x10000000);
}
......
include/dt-bindings/mux/mux.h
View file @ 44197797
......@@ -3,7 +3,7 @@
* This header provides constants for most Multiplexer bindings.
*
* Most Multiplexer bindings specify an idle state. In most cases, the
* the multiplexer can be left as is when idle, and in some cases it can
* multiplexer can be left as is when idle, and in some cases it can
* disconnect the input/output and leave the multiplexer in a high
* impedance state.
*/
......
include/linux/device.h
View file @ 44197797
......@@ -844,6 +844,7 @@ int device_move(struct device *dev, struct device *new_parent,
int device_change_owner(struct device *dev, kuid_t kuid, kgid_t kgid);
const char *device_get_devnode(struct device *dev, umode_t *mode, kuid_t *uid,
kgid_t *gid, const char **tmp);
int device_is_dependent(struct device *dev, void *target);
static inline bool device_supports_offline(struct device *dev)
{
......
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