Commit 44f1bb1f authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10

Move to the header file.
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a644d85a
...@@ -274,15 +274,6 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, ...@@ -274,15 +274,6 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
return true; return true;
} }
struct soc15_allowed_register_entry {
uint32_t hwip;
uint32_t inst;
uint32_t seg;
uint32_t reg_offset;
bool grbm_indexed;
};
static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
......
...@@ -52,6 +52,14 @@ struct soc15_reg_entry { ...@@ -52,6 +52,14 @@ struct soc15_reg_entry {
uint32_t instance; uint32_t instance;
}; };
struct soc15_allowed_register_entry {
uint32_t hwip;
uint32_t inst;
uint32_t seg;
uint32_t reg_offset;
bool grbm_indexed;
};
#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
......
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